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Differential D13654

[mips][ias] Implement ulh macro.
ClosedPublic

Authored by dsanders on Oct 12 2015, 8:03 AM.

Details

Reviewers
vkalintiris
Commits
rG6394ee598e8c: [mips][ias] Implement ulh macro.
rL250414: [mips][ias] Implement ulh macro.
Summary

This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from
failing after the integrated assembler is enabled by default.

Diff Detail

Event Timeline

dsanders updated this revision to Diff 37112.Oct 12 2015, 8:03 AM
dsanders retitled this revision from to [mips][ias] Implement ulh macro..
dsanders updated this object.
dsanders added a reviewer: vkalintiris.
dsanders added a subscriber: llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptOct 12 2015, 8:03 AM
vkalintiris accepted this revision.Oct 14 2015, 8:33 AM
vkalintiris edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Oct 14 2015, 8:33 AM
dsanders closed this revision.Oct 15 2015, 7:54 AM

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
15 lines
3 lines
test/
MC/
Mips/
9 lines
207 lines
3 lines

Diff 37112

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines#include "MipsGenAsmMatcher.inc"
bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, bool expandCondBranches(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool expandDiv(MCInst &Inst, SMLoc IDLoc, bool expandDiv(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions, const bool IsMips64, SmallVectorImpl<MCInst> &Instructions, const bool IsMips64,
const bool Signed); const bool Signed);
bool expandUlhu(MCInst &Inst, SMLoc IDLoc, bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
bool expandUlw(MCInst &Inst, SMLoc IDLoc, bool expandUlw(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
void createNop(bool hasShortDelaySlot, SMLoc IDLoc, void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
▲ Show 20 Lines • Show All 1,654 Lines • ▼ Show 20 Linesbool MipsAsmParser::needsExpansion(MCInst &Inst) {
case Mips::BLTUL: case Mips::BLTUL:
case Mips::BLEUL: case Mips::BLEUL:
case Mips::BGEUL: case Mips::BGEUL:
case Mips::BGTUL: case Mips::BGTUL:
case Mips::SDivMacro: case Mips::SDivMacro:
case Mips::UDivMacro: case Mips::UDivMacro:
case Mips::DSDivMacro: case Mips::DSDivMacro:
case Mips::DUDivMacro: case Mips::DUDivMacro:
case Mips::Ulh:
case Mips::Ulhu: case Mips::Ulhu:
case Mips::Ulw: case Mips::Ulw:
case Mips::NORImm: case Mips::NORImm:
return true; return true;
case Mips::ADDi: case Mips::ADDi:
case Mips::ADDiu: case Mips::ADDiu:
case Mips::SLTi: case Mips::SLTi:
case Mips::SLTiu: case Mips::SLTiu:
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Linesbool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
case Mips::SDivMacro: case Mips::SDivMacro:
return expandDiv(Inst, IDLoc, Instructions, false, true); return expandDiv(Inst, IDLoc, Instructions, false, true);
case Mips::DSDivMacro: case Mips::DSDivMacro:
return expandDiv(Inst, IDLoc, Instructions, true, true); return expandDiv(Inst, IDLoc, Instructions, true, true);
case Mips::UDivMacro: case Mips::UDivMacro:
return expandDiv(Inst, IDLoc, Instructions, false, false); return expandDiv(Inst, IDLoc, Instructions, false, false);
case Mips::DUDivMacro: case Mips::DUDivMacro:
return expandDiv(Inst, IDLoc, Instructions, true, false); return expandDiv(Inst, IDLoc, Instructions, true, false);
case Mips::Ulh:
return expandUlh(Inst, true, IDLoc, Instructions);
case Mips::Ulhu: case Mips::Ulhu:
return expandUlhu(Inst, IDLoc, Instructions); return expandUlh(Inst, false, IDLoc, Instructions);
case Mips::Ulw: case Mips::Ulw:
return expandUlw(Inst, IDLoc, Instructions); return expandUlw(Inst, IDLoc, Instructions);
case Mips::ADDi: case Mips::ADDi:
case Mips::ADDiu: case Mips::ADDiu:
case Mips::ANDi: case Mips::ANDi:
case Mips::NORImm: case Mips::NORImm:
case Mips::ORi: case Mips::ORi:
case Mips::SLTi: case Mips::SLTi:
▲ Show 20 Lines • Show All 995 Lines • ▼ Show 20 Lines else {
emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions); emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, Instructions);
emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions); emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, Instructions);
emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions); emitII(Mips::BREAK, 0x6, 0, IDLoc, Instructions);
} }
emitR(Mips::MFLO, RsReg, IDLoc, Instructions); emitR(Mips::MFLO, RsReg, IDLoc, Instructions);
return false; return false;
} }
bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc, bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) { SmallVectorImpl<MCInst> &Instructions) {
if (hasMips32r6() || hasMips64r6()) { if (hasMips32r6() || hasMips64r6()) {
Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
return false; return false;
} }
warnIfNoMacro(IDLoc); warnIfNoMacro(IDLoc);
const MCOperand &DstRegOp = Inst.getOperand(0); const MCOperand &DstRegOp = Inst.getOperand(0);
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesbool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
} else { } else {
FirstLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue; FirstLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue;
SecondLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1); SecondLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1);
} }
unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg; unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg;
MCInst TmpInst; MCInst TmpInst;
TmpInst.setOpcode(Mips::LBu); TmpInst.setOpcode(Signed ? Mips::LB : Mips::LBu);
TmpInst.addOperand(MCOperand::createReg(FirstLbuDstReg)); TmpInst.addOperand(MCOperand::createReg(FirstLbuDstReg));
TmpInst.addOperand(MCOperand::createReg(LbuSrcReg)); TmpInst.addOperand(MCOperand::createReg(LbuSrcReg));
TmpInst.addOperand(MCOperand::createImm(FirstLbuOffset)); TmpInst.addOperand(MCOperand::createImm(FirstLbuOffset));
Instructions.push_back(TmpInst); Instructions.push_back(TmpInst);
TmpInst.clear(); TmpInst.clear();
TmpInst.setOpcode(Mips::LBu); TmpInst.setOpcode(Mips::LBu);
TmpInst.addOperand(MCOperand::createReg(SecondLbuDstReg)); TmpInst.addOperand(MCOperand::createReg(SecondLbuDstReg));
▲ Show 20 Lines • Show All 2,782 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,821 Lines • ▼ Show 20 Linesdef UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
"divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6; "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
"ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
"ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6; "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
"ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
"ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
"ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions // Arbitrary patterns that map to one or more instructions
▲ Show 20 Lines • Show All 253 Lines • Show Last 20 Lines

test/MC/Mips/mips-expansions-bad.s

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1
# RUN: FileCheck %s < %t1 --check-prefix=32-BIT # RUN: FileCheck %s < %t1 --check-prefix=32-BIT
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \ # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N32-ONLY # RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N32-ONLY
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \ # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 | \
# RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY # RUN: FileCheck %s --check-prefix=64-BIT --check-prefix=N64-ONLY
.text .text
dli $5, 1 dli $5, 1
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
bne $2, 0x100010001, 1332 bne $2, 0x100010001, 1332
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
beq $2, 0x100010001, 1332 beq $2, 0x100010001, 1332
# 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
.set mips32r6 .set mips32r6
ulh $5, 0
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
ulhu $5, 0 ulhu $5, 0
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips32 .set mips32
ulh $5, 1
# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
ulhu $5, 1 ulhu $5, 1
# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips64r6 .set mips64r6
ulh $5, 2
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
ulhu $5, 2 ulhu $5, 2
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips32r6 .set mips32r6
ulw $5, 0 ulw $5, 0
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips32 .set mips32
ulw $5, 1 ulw $5, 1
# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
.set mips64r6 .set mips64r6
ulw $5, 2 ulw $5, 2
# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6

test/MC/Mips/mips-expansions.s

# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
# RUN: FileCheck %s --check-prefix=CHECK-LE # RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \
# RUN: FileCheck %s --check-prefix=CHECK-BE # RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
# Check that the IAS expands macro instructions in the same way as GAS. # Check that the IAS expands macro instructions in the same way as GAS.
# Load address, done by MipsAsmParser::expandLoadAddressReg() # Load address, done by MipsAsmParser::expandLoadAddressReg()
# and MipsAsmParser::expandLoadAddressImm(): # and MipsAsmParser::expandLoadAddressImm():
la $8, 1f la $8, 1f
# CHECK-LE: lui $8, %hi(($tmp0)) # encoding: [A,A,0x08,0x3c] # CHECK-LE: lui $8, %hi(($tmp0)) # encoding: [A,A,0x08,0x3c]
# CHECK-LE: # fixup A - offset: 0, value: %hi(($tmp0)), kind: fixup_Mips_HI16 # CHECK-LE: # fixup A - offset: 0, value: %hi(($tmp0)), kind: fixup_Mips_HI16
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] # CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10]
# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00]
beq $2, 0x10000, 1332 beq $2, 0x10000, 1332
# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c] # CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10] # CHECK-LE: beq $2, $1, 1332 # encoding: [0x4d,0x01,0x41,0x10]
# CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-LE: nop # encoding: [0x00,0x00,0x00,0x00]
# Test ULH with immediate operand.
ulh_imm: # CHECK-LABEL: ulh_imm:
ulh $8, 0
# CHECK-BE: lb $1, 0($zero) # encoding: [0x80,0x01,0x00,0x00]
# CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lb $1, 1($zero) # encoding: [0x01,0x00,0x01,0x80]
# CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 2
# CHECK-BE: lb $1, 2($zero) # encoding: [0x80,0x01,0x00,0x02]
# CHECK-BE: lbu $8, 3($zero) # encoding: [0x90,0x08,0x00,0x03]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lb $1, 3($zero) # encoding: [0x03,0x00,0x01,0x80]
# CHECK-LE: lbu $8, 2($zero) # encoding: [0x02,0x00,0x08,0x90]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 0x8000
# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, -0x8000
# CHECK-BE: lb $1, -32768($zero) # encoding: [0x80,0x01,0x80,0x00]
# CHECK-BE: lbu $8, -32767($zero) # encoding: [0x90,0x08,0x80,0x01]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lb $1, -32767($zero) # encoding: [0x01,0x80,0x01,0x80]
# CHECK-LE: lbu $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x90]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 0x10000
# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 0x18888
# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, -32769
# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff]
# CHECK-BE: ori $1, $1, 32767 # encoding: [0x34,0x21,0x7f,0xff]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK-LE: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 32767
# CHECK-BE: addiu $1, $zero, 32767 # encoding: [0x24,0x01,0x7f,0xff]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: addiu $1, $zero, 32767 # encoding: [0xff,0x7f,0x01,0x24]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
# Test ULH with immediate offset and a source register operand.
ulh_reg: # CHECK-LABEL: ulh_reg:
ulh $8, 0($9)
# CHECK-BE: lb $1, 0($9) # encoding: [0x81,0x21,0x00,0x00]
# CHECK-BE: lbu $8, 1($9) # encoding: [0x91,0x28,0x00,0x01]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lb $1, 1($9) # encoding: [0x01,0x00,0x21,0x81]
# CHECK-LE: lbu $8, 0($9) # encoding: [0x00,0x00,0x28,0x91]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 2($9)
# CHECK-BE: lb $1, 2($9) # encoding: [0x81,0x21,0x00,0x02]
# CHECK-BE: lbu $8, 3($9) # encoding: [0x91,0x28,0x00,0x03]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lb $1, 3($9) # encoding: [0x03,0x00,0x21,0x81]
# CHECK-LE: lbu $8, 2($9) # encoding: [0x02,0x00,0x28,0x91]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 0x8000($9)
# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34]
# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, -0x8000($9)
# CHECK-BE: lb $1, -32768($9) # encoding: [0x81,0x21,0x80,0x00]
# CHECK-BE: lbu $8, -32767($9) # encoding: [0x91,0x28,0x80,0x01]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lb $1, -32767($9) # encoding: [0x01,0x80,0x21,0x81]
# CHECK-LE: lbu $8, -32768($9) # encoding: [0x00,0x80,0x28,0x91]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 0x10000($9)
# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 0x18888($9)
# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88]
# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34]
# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, -32769($9)
# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff]
# CHECK-BE: ori $1, $1, 32767 # encoding: [0x34,0x21,0x7f,0xff]
# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
# CHECK-LE: ori $1, $1, 32767 # encoding: [0xff,0x7f,0x21,0x34]
# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
ulh $8, 32767($9)
# CHECK-BE: addiu $1, $zero, 32767 # encoding: [0x24,0x01,0x7f,0xff]
# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
# CHECK-BE: lb $8, 0($1) # encoding: [0x80,0x28,0x00,0x00]
# CHECK-BE: lbu $1, 1($1) # encoding: [0x90,0x21,0x00,0x01]
# CHECK-BE: sll $8, $8, 8 # encoding: [0x00,0x08,0x42,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: addiu $1, $zero, 32767 # encoding: [0xff,0x7f,0x01,0x24]
# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
# CHECK-LE: lb $8, 1($1) # encoding: [0x01,0x00,0x28,0x80]
# CHECK-LE: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
# Test ULHU with immediate operand. # Test ULHU with immediate operand.
ulhu_imm: # CHECK-LABEL: ulhu_imm:
ulhu $8, 0 ulhu $8, 0
# CHECK-BE: lbu $1, 0($zero) # encoding: [0x90,0x01,0x00,0x00] # CHECK-BE: lbu $1, 0($zero) # encoding: [0x90,0x01,0x00,0x00]
# CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01] # CHECK-BE: lbu $8, 1($zero) # encoding: [0x90,0x08,0x00,0x01]
# CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00] # CHECK-BE: sll $1, $1, 8 # encoding: [0x00,0x01,0x0a,0x00]
# CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25] # CHECK-BE: or $8, $8, $1 # encoding: [0x01,0x01,0x40,0x25]
# CHECK-LE: lbu $1, 1($zero) # encoding: [0x01,0x00,0x01,0x90] # CHECK-LE: lbu $1, 1($zero) # encoding: [0x01,0x00,0x01,0x90]
# CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90] # CHECK-LE: lbu $8, 0($zero) # encoding: [0x00,0x00,0x08,0x90]
# CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00] # CHECK-LE: sll $1, $1, 8 # encoding: [0x00,0x0a,0x01,0x00]
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test/MC/Mips/set-nomacro.s

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines# CHECK-NOT: warning: macro instruction expanded into multiple instructions
bgt $0, $8, local_label bgt $0, $8, local_label
bgt $0, $0, local_label bgt $0, $0, local_label
bgtu $7, $8, local_label bgtu $7, $8, local_label
bgtu $7, $0, local_label bgtu $7, $0, local_label
bgtu $0, $8, local_label bgtu $0, $8, local_label
bgtu $0, $0, local_label bgtu $0, $0, local_label
ulh $5, 0
ulhu $5, 0 ulhu $5, 0
ulw $8, 2 ulw $8, 2
ulw $8, 0x8000 ulw $8, 0x8000
ulw $8, 2($9) ulw $8, 2($9)
ulw $8, 0x8000($9) ulw $8, 0x8000($9)
jal foo jal foo
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# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
bgtu $7, $0, local_label bgtu $7, $0, local_label
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
bgtu $0, $8, local_label bgtu $0, $8, local_label
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
bgtu $0, $0, local_label bgtu $0, $0, local_label
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
ulh $5, 0
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
ulhu $5, 0 ulhu $5, 0
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
ulw $8, 2 ulw $8, 2
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
ulw $8, 0x8000 ulw $8, 0x8000
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
ulw $8, 2($9) ulw $8, 2($9)
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