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Differential D13594

[mips] Allowed dla instructions on 32-bit architectures.
ClosedPublic

Authored by s.egerton on Oct 9 2015, 7:52 AM.

Details

Reviewers
dsanders
vkalintiris
Commits
rG2455701117c1: [mips] Allowed dla instructions on 32-bit architectures.
rL258400: [mips] Allowed dla instructions on 32-bit architectures.
Summary

This is now the same as the behaviour of the GNU assembler. This was done
as it is required in order to build the Linux kernel with the integrated
assembler enabled.

Diff Detail

Event Timeline

s.egerton updated this revision to Diff 36948.Oct 9 2015, 7:52 AM
s.egerton retitled this revision from to [mips] Allowed dla instructions on 32-bit architectures..
s.egerton updated this object.
s.egerton added reviewers: dsanders, vkalintiris.
s.egerton added a subscriber: llvm-commits.
vkalintiris requested changes to this revision.Oct 9 2015, 3:25 PM
vkalintiris edited edge metadata.

Could you add a few tests to check this change?

This revision now requires changes to proceed.Oct 9 2015, 3:25 PM
s.egerton updated this revision to Diff 41057.Nov 24 2015, 9:09 AM
s.egerton edited edge metadata.

I've now added test cases which test everything that is tested for dla on 64-bit architecture. I had to update the patch to then pass these tests.

Herald added a subscriber: dsanders. · View Herald TranscriptNov 24 2015, 9:09 AM
s.egerton added a comment.Dec 18 2015, 4:39 AM

ping

s.egerton added a comment.Jan 18 2016, 7:26 AM

ping

vkalintiris accepted this revision.Jan 19 2016, 2:48 AM
vkalintiris edited edge metadata.

LGTM, but clang-format the sources before committing.

test/MC/Mips/macro-dla-32bit.s
2

Do we really need the -gpsize option?

This revision is now accepted and ready to land.Jan 19 2016, 2:48 AM
s.egerton closed this revision.Jan 21 2016, 7:14 AM

Revision Contents

PathSize
include/
llvm/
MC/
6 lines
lib/
Target/
Mips/
AsmParser/
15 lines
test/
MC/
Mips/
228 lines

Diff 41057

include/llvm/MC/MCRegisterInfo.h

Show First 20 Lines • Show All 434 Lines • ▼ Show 20 Linespublic:
} }
/// \brief Returns true if RegB is a super-register of RegA or if /// \brief Returns true if RegB is a super-register of RegA or if
/// RegB == RegA. /// RegB == RegA.
bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
return RegA == RegB || isSuperRegister(RegA, RegB); return RegA == RegB || isSuperRegister(RegA, RegB);
} }
/// \brief Returns true if RegB is a super-register or sub-register of RegA
/// or if RegB == RegA.
bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
}
}; };
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register List Iterators // Register List Iterators
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MCRegisterInfo provides lists of super-registers, sub-registers, and // MCRegisterInfo provides lists of super-registers, sub-registers, and
// aliasing registers. Use these iterator classes to traverse the lists. // aliasing registers. Use these iterator classes to traverse the lists.
▲ Show 20 Lines • Show All 239 Lines • Show Last 20 Lines

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 2,207 Lines • ▼ Show 20 Linesbool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
bool UseSrcReg = false; bool UseSrcReg = false;
if (SrcReg != Mips::NoRegister) if (SrcReg != Mips::NoRegister)
UseSrcReg = true; UseSrcReg = true;
unsigned TmpReg = DstReg; unsigned TmpReg = DstReg;
if (UseSrcReg && (DstReg == SrcReg)) { if (UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
// At this point we need AT to perform the expansions and we exit if it is // At this point we need AT to perform the expansions and we exit if it is
// not available. // not available.
unsigned ATReg = getATReg(IDLoc); unsigned ATReg = getATReg(IDLoc);
if (!ATReg) if (!ATReg)
return true; return true;
TmpReg = ATReg; TmpReg = ATReg;
} }
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines if (Is32BitAddress && ABI.ArePtrs64bit()) {
// We currently can't do this because we depend on the equality // We currently can't do this because we depend on the equality
// operator and N64 can end up with a GPR32/GPR64 mismatch. // operator and N64 can end up with a GPR32/GPR64 mismatch.
Error(IDLoc, "la used to load 64-bit address"); Error(IDLoc, "la used to load 64-bit address");
// Continue as if we had 'dla' instead. // Continue as if we had 'dla' instead.
Is32BitAddress = false; Is32BitAddress = false;
} }
// dla requires 64-bit addresses. // dla requires 64-bit addresses.
if (!Is32BitAddress && !ABI.ArePtrs64bit()) { if (!Is32BitAddress && !hasMips3()) {
Error(IDLoc, "instruction requires a 64-bit architecture"); Error(IDLoc, "instruction requires a 64-bit architecture");
return true; return true;
} }
if (!Offset.isImm()) if (!Offset.isImm())
return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg, return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg,
Is32BitAddress, IDLoc, Instructions); Is32BitAddress, IDLoc, Instructions);
if (!ABI.ArePtrs64bit()) {
// Continue as if we had 'la' whether we had 'la' or 'dla'.
Is32BitAddress = true;
}
return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true, return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true,
IDLoc, Instructions); IDLoc, Instructions);
} }
bool MipsAsmParser::loadAndAddSymbolAddress( bool MipsAsmParser::loadAndAddSymbolAddress(
const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym,
SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
warnIfNoMacro(IDLoc); warnIfNoMacro(IDLoc);
Show All 14 Lines if (ABI.ArePtrs64bit() && isGP64bit()) {
if (!ATReg) if (!ATReg)
return true; return true;
const MipsMCExpr *HighestExpr = MipsMCExpr::create( const MipsMCExpr *HighestExpr = MipsMCExpr::create(
MCSymbolRefExpr::VK_Mips_HIGHEST, Symbol, getContext()); MCSymbolRefExpr::VK_Mips_HIGHEST, Symbol, getContext());
const MipsMCExpr *HigherExpr = MipsMCExpr::create( const MipsMCExpr *HigherExpr = MipsMCExpr::create(
MCSymbolRefExpr::VK_Mips_HIGHER, Symbol, getContext()); MCSymbolRefExpr::VK_Mips_HIGHER, Symbol, getContext());
if (UseSrcReg && (DstReg == SrcReg)) { if (UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
// If $rs is the same as $rd: // If $rs is the same as $rd:
// (d)la $rd, sym($rd) => lui $at, %highest(sym) // (d)la $rd, sym($rd) => lui $at, %highest(sym)
// daddiu $at, $at, %higher(sym) // daddiu $at, $at, %higher(sym)
// dsll $at, $at, 16 // dsll $at, $at, 16
// daddiu $at, $at, %hi(sym) // daddiu $at, $at, %hi(sym)
// dsll $at, $at, 16 // dsll $at, $at, 16
// daddiu $at, $at, %lo(sym) // daddiu $at, $at, %lo(sym)
// daddu $rd, $at, $rd // daddu $rd, $at, $rd
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesbool MipsAsmParser::loadAndAddSymbolAddress(
// (d)la $rd, sym($rd) => lui $at, %hi(sym) // (d)la $rd, sym($rd) => lui $at, %hi(sym)
// ori $at, $at, %lo(sym) // ori $at, $at, %lo(sym)
// addu $rd, $at, $rd // addu $rd, $at, $rd
// Otherwise, if the $rs is different from $rd or if $rs isn't specified: // Otherwise, if the $rs is different from $rd or if $rs isn't specified:
// (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym) // (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym)
// ori $rd, $rd, %lo(sym) // ori $rd, $rd, %lo(sym)
// (addu $rd, $rd, $rs) // (addu $rd, $rd, $rs)
unsigned TmpReg = DstReg; unsigned TmpReg = DstReg;
if (UseSrcReg && (DstReg == SrcReg)) { if (UseSrcReg && getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
// If $rs is the same as $rd, we need to use AT. // If $rs is the same as $rd, we need to use AT.
// If it is not available we exit. // If it is not available we exit.
unsigned ATReg = getATReg(IDLoc); unsigned ATReg = getATReg(IDLoc);
if (!ATReg) if (!ATReg)
return true; return true;
TmpReg = ATReg; TmpReg = ATReg;
} }
emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, Instructions); emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, Instructions);
emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), IDLoc, emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), IDLoc,
Instructions); Instructions);
if (UseSrcReg) if (UseSrcReg)
emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Instructions); emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, Instructions);
else else
assert(DstReg == TmpReg); assert(getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
return false; return false;
} }
bool MipsAsmParser::expandUncondBranchMMPseudo( bool MipsAsmParser::expandUncondBranchMMPseudo(
MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 && assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
"unexpected number of operands"); "unexpected number of operands");
▲ Show 20 Lines • Show All 3,701 Lines • Show Last 20 Lines

test/MC/Mips/macro-dla-32bit.s

  • This file was added.
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 \
# RUN: -gpsize=0 | FileCheck %s
vkalintirisUnsubmitted
Not Done
ReplyInline Actions

Do we really need the -gpsize option?

vkalintiris: Do we really need the -gpsize option?
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: -gpsize=0 | FileCheck %s
.set mips64r2
dla $5, 0x00000001 # CHECK: addiu $5, $zero, 1 # encoding: [0x24,0x05,0x00,0x01]
dla $5, 0x00000002 # CHECK: addiu $5, $zero, 2 # encoding: [0x24,0x05,0x00,0x02]
dla $5, 0x00004000 # CHECK: addiu $5, $zero, 16384 # encoding: [0x24,0x05,0x40,0x00]
dla $5, 0x00008000 # CHECK: ori $5, $zero, 32768 # encoding: [0x34,0x05,0x80,0x00]
dla $5, 0xffffffff # CHECK: addiu $5, $zero, -1 # encoding: [0x24,0x05,0xff,0xff]
dla $5, 0xfffffffe # CHECK: addiu $5, $zero, -2 # encoding: [0x24,0x05,0xff,0xfe]
dla $5, 0xffffc000 # CHECK: addiu $5, $zero, -16384 # encoding: [0x24,0x05,0xc0,0x00]
dla $5, 0xffff8000 # CHECK: addiu $5, $zero, -32768 # encoding: [0x24,0x05,0x80,0x00]
dla $5, 0x00010000 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
dla $5, 0x00020000 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
dla $5, 0x40000000 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
dla $5, 0x80000000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
dla $5, 0xffff0000 # CHECK: lui $5, 65535 # encoding: [0x3c,0x05,0xff,0xff]
dla $5, 0xfffe0000 # CHECK: lui $5, 65534 # encoding: [0x3c,0x05,0xff,0xfe]
dla $5, 0xc0000000 # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00]
dla $5, 0x80000000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
dla $5, 0x00010001 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
dla $5, 0x00020001 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
dla $5, 0x40000001 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
dla $5, 0x80000001 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
dla $5, 0x00010002 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
dla $5, 0x00020002 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
dla $5, 0x40000002 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
dla $5, 0x80000002 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
dla $5, 0x00014000 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
dla $5, 0x00024000 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
dla $5, 0x40004000 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
dla $5, 0x80004000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
dla $5, 0x00018000 # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0x00028000 # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0x40008000 # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0xffff4000 # CHECK: lui $5, 65535 # encoding: [0x3c,0x05,0xff,0xff]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
dla $5, 0xfffe8000 # CHECK: lui $5, 65534 # encoding: [0x3c,0x05,0xff,0xfe]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0xc0008000 # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
dla $5, 0x00000001($6) # CHECK: addiu $5, $6, 1 # encoding: [0x24,0xc5,0x00,0x01]
dla $5, 0x00000002($6) # CHECK: addiu $5, $6, 2 # encoding: [0x24,0xc5,0x00,0x02]
dla $5, 0x00004000($6) # CHECK: addiu $5, $6, 16384 # encoding: [0x24,0xc5,0x40,0x00]
dla $5, 0x00008000($6) # CHECK: ori $5, $zero, 32768 # encoding: [0x34,0x05,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xffffffff($6) # CHECK: addiu $5, $6, -1 # encoding: [0x24,0xc5,0xff,0xff]
dla $5, 0xfffffffe($6) # CHECK: addiu $5, $6, -2 # encoding: [0x24,0xc5,0xff,0xfe]
dla $5, 0xffffc000($6) # CHECK: addiu $5, $6, -16384 # encoding: [0x24,0xc5,0xc0,0x00]
dla $5, 0xffff8000($6) # CHECK: addiu $5, $6, -32768 # encoding: [0x24,0xc5,0x80,0x00]
dla $5, 0x00010000($6) # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00020000($6) # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x40000000($6) # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80000000($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xffff0000($6) # CHECK: lui $5, 65535 # encoding: [0x3c,0x05,0xff,0xff]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xfffe0000($6) # CHECK: lui $5, 65534 # encoding: [0x3c,0x05,0xff,0xfe]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xc0000000($6) # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80000000($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00010001($6) # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00020001($6) # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x40000001($6) # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80000001($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 1 # encoding: [0x34,0xa5,0x00,0x01]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00010002($6) # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00020002($6) # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x40000002($6) # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80000002($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 2 # encoding: [0x34,0xa5,0x00,0x02]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00014000($6) # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00024000($6) # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x40004000($6) # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80004000($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00018000($6) # CHECK: lui $5, 1 # encoding: [0x3c,0x05,0x00,0x01]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x00028000($6) # CHECK: lui $5, 2 # encoding: [0x3c,0x05,0x00,0x02]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x40008000($6) # CHECK: lui $5, 16384 # encoding: [0x3c,0x05,0x40,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80008000($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xffff4000($6) # CHECK: lui $5, 65535 # encoding: [0x3c,0x05,0xff,0xff]
# CHECK: ori $5, $5, 16384 # encoding: [0x34,0xa5,0x40,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xfffe8000($6) # CHECK: lui $5, 65534 # encoding: [0x3c,0x05,0xff,0xfe]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0xc0008000($6) # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
dla $5, 0x80008000($6) # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
# CHECK: addu $5, $5, $6 # encoding: [0x00,0xa6,0x28,0x21]
# There are no further interesting immediates.
symbol: # CHECK-LABEL: symbol:
.extern extern_sym
.option pic0 # CHECK-LABEL: .option pic0
dla $5, extern_sym
# CHECK: lui $5, %hi(extern_sym) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo(extern_sym) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym), kind: fixup_Mips_LO16
dla $5, extern_sym($8)
# CHECK: lui $5, %hi(extern_sym) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo(extern_sym) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym), kind: fixup_Mips_LO16
# CHECK: addu $5, $5, $8 # encoding: [0x00,0xa8,0x28,0x21]
dla $5, extern_sym($5)
# CHECK: lui $1, %hi(extern_sym) # encoding: [0x3c,0x01,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym), kind: fixup_Mips_HI16
# CHECK: addiu $1, $1, %lo(extern_sym) # encoding: [0x24,0x21,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym), kind: fixup_Mips_LO16
# CHECK: addu $5, $1, $5 # encoding: [0x00,0x25,0x28,0x21]
dla $5, extern_sym+8
# CHECK: lui $5, %hi(extern_sym+8) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym+8), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo(extern_sym+8) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym+8), kind: fixup_Mips_LO16
dla $5, extern_sym+8($8)
# CHECK: lui $5, %hi(extern_sym+8) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym+8), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo(extern_sym+8) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym+8), kind: fixup_Mips_LO16
# CHECK: addu $5, $5, $8 # encoding: [0x00,0xa8,0x28,0x21]
dla $5, extern_sym-8($5)
# CHECK: lui $1, %hi(extern_sym-8) # encoding: [0x3c,0x01,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym-8), kind: fixup_Mips_HI16
# CHECK: addiu $1, $1, %lo(extern_sym-8) # encoding: [0x24,0x21,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym-8), kind: fixup_Mips_LO16
# CHECK: addu $5, $1, $5 # encoding: [0x00,0x25,0x28,0x21]
dla $5, extern_sym-8
# CHECK: lui $5, %hi(extern_sym-8) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym-8), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo(extern_sym-8) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym-8), kind: fixup_Mips_LO16
dla $5, extern_sym-8($8)
# CHECK: lui $5, %hi(extern_sym-8) # encoding: [0x3c,0x05,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym-8), kind: fixup_Mips_HI16
# CHECK: addiu $5, $5, %lo(extern_sym-8) # encoding: [0x24,0xa5,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym-8), kind: fixup_Mips_LO16
# CHECK: addu $5, $5, $8 # encoding: [0x00,0xa8,0x28,0x21]
dla $5, extern_sym-8($5)
# CHECK: lui $1, %hi(extern_sym-8) # encoding: [0x3c,0x01,A,A]
# CHECK: # fixup A - offset: 0, value: %hi(extern_sym-8), kind: fixup_Mips_HI16
# CHECK: addiu $1, $1, %lo(extern_sym-8) # encoding: [0x24,0x21,A,A]
# CHECK: # fixup A - offset: 0, value: %lo(extern_sym-8), kind: fixup_Mips_LO16
# CHECK: addu $5, $1, $5 # encoding: [0x00,0x25,0x28,0x21]
.option pic2