[LLDB][MIPS] microMIPS load/store instruction emulation for hardware watchpoints

lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

g_opcodes[] =
         { "LWC1",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWC1  ft, offset(base)" },
         { "LWC2",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWC2  rt, offset(base)" },
         { "LWE",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWE   rt, offset(base)" },
         { "LWL",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWL   rt, offset(base)" },
         { "LWLE",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWLE  rt, offset(base)" },
         { "LWR",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWR   rt, offset(base)" },
         { "LWRE",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LWRE  rt, offset(base)" },
         { "LWXC1",      &EmulateInstructionMIPS::Emulate_LDST_Reg,          "LWXC1 fd, index (base)" },
+        { "LLX",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LLX   rt, offset(base)" },
+        { "LLXE",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LLXE  rt, offset(base)" },
+        { "LLDX",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "LLDX  rt, offset(base)" },
 
         { "SB",         &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SB    rt, offset(base)" },
         { "SBE",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SBE   rt, offset(base)" },
         { "SC",         &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SC    rt, offset(base)" },
         { "SCE",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SCE   rt, offset(base)" },
         { "SCD",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SCD   rt, offset(base)" },
         { "SD",         &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SD    rt, offset(base)" },
         { "SDL",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SDL   rt, offset(base)" },
         { "SDR",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SDR   rt, offset(base)" },
         { "SDC1",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SDC1  ft, offset(base)" },
         { "SDC2",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SDC2  rt, offset(base)" },
         { "SDXC1",      &EmulateInstructionMIPS::Emulate_LDST_Reg,          "SDXC1 fs, index(base)"  },
         { "SH",         &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SH    rt, offset(base)" },
         { "SHE",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SHE   rt, offset(base)" },
         { "SUXC1",      &EmulateInstructionMIPS::Emulate_LDST_Reg,          "SUXC1 fs, index (base)" },
         { "SWC1",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWC1  ft, offset(base)" },
         { "SWC2",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWC2  rt, offset(base)" },
         { "SWE",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWE   rt, offset(base)" },
         { "SWL",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWL   rt, offset(base)" },
         { "SWLE",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWLE  rt, offset(base)" },
         { "SWR",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWR   rt, offset(base)" },
         { "SWRE",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SWRE  rt, offset(base)" },
         { "SWXC1",      &EmulateInstructionMIPS::Emulate_LDST_Reg,          "SWXC1 fs, index (base)" },
+        { "SCX",        &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SCX   rt, offset(base)" },
+        { "SCXE",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SCXE  rt, offset(base)" },
+        { "SCDX",       &EmulateInstructionMIPS::Emulate_LDST_Imm,          "SCDX  rt, offset(base)" },
+
+        //----------------------------------------------------------------------
+        // MicroMIPS Load/Store instructions
+        //----------------------------------------------------------------------
+        { "LBU16_MM",      &EmulateInstructionMIPS::Emulate_LDST_Imm,       "LBU16 rt, decoded_offset(base)"       },
+        { "LHU16_MM",      &EmulateInstructionMIPS::Emulate_LDST_Imm,       "LHU16 rt, left_shifted_offset(base)"  },
+        { "LW16_MM",       &EmulateInstructionMIPS::Emulate_LDST_Imm,       "LW16  rt, left_shifted_offset(base)"  },
+        { "LWGP_MM",       &EmulateInstructionMIPS::Emulate_LDST_Imm,       "LWGP  rt, left_shifted_offset(gp)"    },
+        { "SH16_MM",       &EmulateInstructionMIPS::Emulate_LDST_Imm,       "SH16  rt, left_shifted_offset(base)"  },
+        { "SW16_MM",       &EmulateInstructionMIPS::Emulate_LDST_Imm,       "SW16  rt, left_shifted_offset(base)"  },
+        { "SW_MM",         &EmulateInstructionMIPS::Emulate_LDST_Imm,       "SWSP  rt, left_shifted_offset(base)"  },
+        { "SB16_MM",       &EmulateInstructionMIPS::Emulate_LDST_Imm,       "SB16  rt, offset(base)"               },
 
         //----------------------------------------------------------------------
         // Branch instructions
         //----------------------------------------------------------------------
         { "BEQ",        &EmulateInstructionMIPS::Emulate_BEQ,         "BEQ rs,rt,offset"          },
         { "BNE",        &EmulateInstructionMIPS::Emulate_BNE,         "BNE rs,rt,offset"          },
         { "BEQL",       &EmulateInstructionMIPS::Emulate_BEQL,        "BEQL rs,rt,offset"         },
         { "BNEL",       &EmulateInstructionMIPS::Emulate_BNEL,        "BNEL rs,rt,offset"         },

 }
 
 bool
 EmulateInstructionMIPS::Emulate_SWSP (llvm::MCInst& insn)
 {
     bool success = false;
     uint32_t imm5 = insn.getOperand(2).getImm();
     uint32_t src, base;
+    Context bad_vaddr_context;
+    uint32_t address;
 
     src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
     base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
 
-    // We look for sp based non-volatile register stores.
-    if (base == dwarf_sp_mips && nonvolatile_reg_p (src))
-    {
-        uint32_t address;
-        RegisterInfo reg_info_base;
-        RegisterInfo reg_info_src;
 
-        if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)
-            || !GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src))
-            return false;
+    if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base))
 
-        // read SP
-        address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
-        if (!success)
-            return false;
+    // read base register
 
-        // destination address
-        address = address + imm5;
 
+    // We use bad_vaddr_context to store base address which is used by H/W watchpoint
+    // Set the bad_vaddr register with base address used in the instruction
+    bad_vaddr_context.type = eContextInvalid;
+    WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address);
+
+    // We look for sp based non-volatile register stores.
+    if (base == dwarf_sp_mips && nonvolatile_reg_p (src))
+    {
+        uint32_t address;
+        RegisterInfo reg_info_base;
+        RegisterInfo reg_info_src;
+
         Context context;
         RegisterValue data_src;
         context.type = eContextPushRegisterOnStack;
         context.SetRegisterToRegisterPlusOffset (reg_info_src, reg_info_base, 0);
 
         uint8_t buffer [RegisterValue::kMaxRegisterByteSize];
         Error error;
 

 
 bool
 EmulateInstructionMIPS::Emulate_LWSP (llvm::MCInst& insn)
 {
     bool success = false;
     uint32_t src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
     uint32_t base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg());
     uint32_t imm5 = insn.getOperand(2).getImm();
+    Context bad_vaddr_context;
 
-    if (base == dwarf_sp_mips && nonvolatile_reg_p (src))
-    {
-        RegisterValue data_src;
-        RegisterInfo reg_info_src;
-
-        if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src))
-            return false;
+    RegisterInfo reg_info_base;
+    if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base))
 
-        uint32_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
-        if (!success)
-            return false;
+    // read base register
 
-        base_address = base_address + imm5;
 
+    // We use bad_vaddr_context to store base address which is used by H/W watchpoint
+    // Set the bad_vaddr register with base address used in the instruction
+    bad_vaddr_context.type = eContextInvalid;
+    WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, base_address);
+
+    if (base == dwarf_sp_mips && nonvolatile_reg_p (src))
+    {
+        RegisterValue data_src;
+        RegisterInfo reg_info_src;
+
+        if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + src, reg_info_src))
+            return false;
+
         Context context;
         context.type = eContextPopRegisterOffStack;
         context.SetAddress (base_address);
 
         if (!WriteRegister (context, &reg_info_src, data_src))
             return false;
 
         return true;