[mips] Handle undef when extracting subregs from FP64 registers.

[dsanders]

Summary

This removes unnecessary instructions when extracting from an undefined register
and also fixes a crash for O32 when passing undef to a double argument in
held in integer registers.

[vkalintiris]

check-llvm fails on the following tests:

LLVM :: CodeGen/Mips/buildpairextractelementf64.ll
LLVM :: CodeGen/Mips/fcopysign.ll
LLVM :: CodeGen/Mips/fp16instrinsmc.ll
LLVM :: CodeGen/Mips/fp64a.ll
LLVM :: CodeGen/Mips/fpxx.ll
LLVM :: CodeGen/Mips/i64arg.ll
LLVM :: CodeGen/Mips/mips16_32_8.ll
LLVM :: CodeGen/Mips/mno-ldc1-sdc1.ll
LLVM :: CodeGen/Mips/o32_cc.ll
LLVM :: CodeGen/Mips/o32_cc_byval.ll

lib/Target/Mips/MipsSEFrameLowering.cpp

324 ↗

(On Diff #36612)

We should get the debug location from I->getDebugLoc(), right?

[dsanders]

Check operands are registers before testing for undef.

[dsanders]

lib/Target/Mips/MipsSEFrameLowering.cpp

324 ↗

(On Diff #37028)

IMPLICIT_DEF doesn't generate any code so it should affect the debug info but I've made this change anyway.

[vkalintiris]

LGTM.

llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp

 /// This method expands the same instruction that MipsSEInstrInfo::
 /// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
 /// available and the case where the ABI is FP64A. It is implemented here
 /// because frame indexes are eliminated before MipsSEInstrInfo::
 /// expandExtractElementF64 is called.
 bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator I,
                                            bool FP64) const {
+  const MachineOperand &Op1 = I->getOperand(1);
+  const MachineOperand &Op2 = I->getOperand(2);
+
+  if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
+    unsigned DstReg = I->getOperand(0).getReg();
+    BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
+    return true;
+  }
+
   // For fpxx and when mfhc1 is not available, use:
   //   spill + reload via ldc1
   //
   // The case where dmfc1 is available doesn't need to be handled here
   // because it never creates a ExtractElementF64 node.
   //
   // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
   // for odd-numbered double precision values (because the lower 32-bits is
   // transferred with mfc1 which is redirected to the upper half of the even
   // register). Unfortunately, we have to make this decision before register
   // allocation so for now we use a spill/reload sequence for all
   // double-precision values in regardless of being an odd/even register.
 
   if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
       (FP64 && !Subtarget.useOddSPReg())) {
     unsigned DstReg = I->getOperand(0).getReg();
-    unsigned SrcReg = I->getOperand(1).getReg();
-    unsigned N = I->getOperand(2).getImm();
+    unsigned SrcReg = Op1.getReg();
+    unsigned N = Op2.getImm();
     int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
 
     // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
     // the cases where mfhc1 is not available). 64-bit architectures and
     // MIPS32r2 or later can use FGR64 though.
     assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
            !Subtarget.isFP64bit());
 
     const TargetRegisterClass *RC =
         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
     const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
 
     // We re-use the same spill slot each time so that the stack frame doesn't
     // grow too much in functions with a large number of moves.
     int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
-    TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC,
-                        &RegInfo, 0);
+    TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
     TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
     return true;
   }
 
   return false;
 }
 
 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)

llvm/trunk/test/CodeGen/Mips/llvm-ir/call.ll

 ; Test the 'call' instruction and the tailcall variant.
 
 ; FIXME: We should remove the need for -enable-mips-tail-calls
 ; RUN: llc -march=mips   -mcpu=mips32   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips   -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips   -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
 ; RUN: llc -march=mips64 -mcpu=mips4    -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64   -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 ; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
 
 declare void @extern_void_void()

 ; ALL-LABEL: tail_indirect_call_float_void:
 
 ; ALL:           move $25, $4
 ; ALL:           jr $25
 
   %1 = tail call float %addr()
   ret float %1
 }
+
+; Check that passing undef as a double value doesn't cause machine code errors
+; for FP64.
+declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align 2
+
+define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 {
+; ALL-LABEL: thunk_undef_double:
+; O32: # implicit-def: A2
+; O32: # implicit-def: A3
+; ALL: jr $25
+  tail call void @undef_double(i32 undef, double undef) #8
+  ret void
+}