[mips] Use PredicateControl for the MSA ASE instructions. NFC.

[vkalintiris]

LGTM.

lib/Target/Mips/MipsInstrInfo.td

 def NotInMicroMips :  Predicate<"!Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"!FeatureMicroMips">;
 def IsLE           :  Predicate<"Subtarget->isLittle()">;
 def IsBE           :  Predicate<"!Subtarget->isLittle()">;
 def IsNotNaCl    :    Predicate<"!Subtarget->isTargetNaCl()">;
 def UseTCCInDIV    :  AssemblerPredicate<"FeatureUseTCCInDIV">;
 def HasEVA       :    Predicate<"Subtarget->hasEVA()">,
                       AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
+def HasMSA : Predicate<"Subtarget->hasMSA()">,
+             AssemblerPredicate<"FeatureMSA">;
+
 
 //===----------------------------------------------------------------------===//
 // Mips GPR size adjectives.
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 
 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }

 }
 
 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
 }
 
+class ASE_MSA {
+  list<Predicate> InsnPredicates = [HasMSA];
+}
+
+class ASE_MSA64 {
+  list<Predicate> InsnPredicates = [HasMSA, HasMips64];
+}
+
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
   let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
 }
 
 //===----------------------------------------------------------------------===//
 

lib/Target/Mips/MipsMSAInstrFormats.td

 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
-def HasMSA : Predicate<"Subtarget->hasMSA()">,
-             AssemblerPredicate<"FeatureMSA">;
-
-class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
-  let Predicates = [HasMSA];
+class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
+                PredicateControl, ASE_MSA {
+  let EncodingPredicates = [HasStdEnc];
   let Inst{31-26} = 0b011110;
 }
 
-class MSA64Inst : MSAInst {
-  let Predicates = [HasMSA, HasMips64];
-}
-
 class MSACBranch : MSAInst {
   let Inst{31-26} = 0b010001;
 }
 
 class MSASpecial : MSAInst {
   let Inst{31-26} = 0b000000;
 }
 
-class MSA64Special : MSA64Inst {
-  let Inst{31-26} = 0b000000;
-}
-
 class MSAPseudo<dag outs, dag ins, list<dag> pattern,
                 InstrItinClass itin = IIPseudo>:
   MipsPseudo<outs, ins, pattern, itin> {
   let Predicates = [HasMSA];
 }
 
 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
   bits<5> ws;
class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
 
   let Inst{25-18} = major;
   let Inst{17-16} = df;
   let Inst{15-11} = rs;
   let Inst{10-6} = wd;
   let Inst{5-0} = minor;
 }
 
-class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst {
+class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
   bits<5> rs;
   bits<5> wd;
 
   let Inst{25-18} = major;
   let Inst{17-16} = df;
   let Inst{15-11} = rs;
   let Inst{10-6} = wd;
   let Inst{5-0} = minor;
class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
   let Inst{25-22} = major;
   let Inst{21-18} = 0b1100;
   let Inst{17-16} = n{1-0};
   let Inst{15-11} = ws;
   let Inst{10-6} = rd;
   let Inst{5-0} = minor;
 }
 
-class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
+class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
   bits<4> n;
   bits<5> ws;
   bits<5> rd;
 
   let Inst{25-22} = major;
   let Inst{21-17} = 0b11100;
   let Inst{16} = n{0};
   let Inst{15-11} = ws;
class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
   let Inst{25-22} = major;
   let Inst{21-18} = 0b1100;
   let Inst{17-16} = n{1-0};
   let Inst{15-11} = rs;
   let Inst{10-6} = wd;
   let Inst{5-0} = minor;
 }
 
-class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
+class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
   bits<6> n;
   bits<5> rs;
   bits<5> wd;
 
   let Inst{25-22} = major;
   let Inst{21-17} = 0b11100;
   let Inst{16} = n{0};
   let Inst{15-11} = rs;
class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
   let Inst{15-11} = rd;
   let Inst{10-8} = 0b000;
   let Inst{7-6} = sa;
   let Inst{5-0} = minor;
 }
 
-class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special {
+class SPECIAL_DLSA_FMT<bits<6> minor>: MSASpecial {
   bits<5> rs;
   bits<5> rt;
   bits<5> rd;
   bits<2> sa;
 
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
   let Inst{15-11} = rd;
   let Inst{10-8} = 0b000;
   let Inst{7-6} = sa;
   let Inst{5-0} = minor;
 }

lib/Target/Mips/MipsMSAInstrInfo.td

 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
 
 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
-def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
+def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
 
 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
-def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
+def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC, ASE_MSA64;
 
 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
 
 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
 
 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;

 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
 
 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
 
 def FILL_B : FILL_B_ENC, FILL_B_DESC;
 def FILL_H : FILL_H_ENC, FILL_H_DESC;
 def FILL_W : FILL_W_ENC, FILL_W_DESC;
-def FILL_D : FILL_D_ENC, FILL_D_DESC;
+def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
 
 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
 
 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;

 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
 
 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
-def INSERT_D : INSERT_D_ENC, INSERT_D_DESC;
+def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
 
 // INSERT_FW_PSEUDO defined after INSVE_W
 // INSERT_FD_PSEUDO defined after INSVE_D
 
 // There is a fourth operand that is not present in the encoding. Use a
 // custom decoder to get a chance to add it.
 let DecoderMethod = "DecodeINSVE_DF" in {
   def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;

 def LD_D: LD_D_ENC, LD_D_DESC;
 
 def LDI_B : LDI_B_ENC, LDI_B_DESC;
 def LDI_H : LDI_H_ENC, LDI_H_DESC;
 def LDI_W : LDI_W_ENC, LDI_W_DESC;
 def LDI_D : LDI_D_ENC, LDI_D_DESC;
 
 def LSA : LSA_ENC, LSA_DESC;
-def DLSA : DLSA_ENC, DLSA_DESC;
+def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
 
 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
 
 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
 
 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;