[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation

[zoran.jovanovic]

Test files renamed and changed usage of predicates.

[dsanders]

LGTM with a few nits.

I noticed you don't actually use DSPR3 yet but I expect will change in the next few patches.

lib/Target/Mips/MicroMipsDSPInstrFormats.td

1–2 ↗

(On Diff #35093)

Unfortunately, this has to be a single line and we have to fit into 80 cols as well. The '-*- tablegen -*-' is used by editors to configure for the specified language.

The 'Micromips DSP' part is probably the best bit to remove.

13 ↗

(On Diff #35093)

HasDSP is not an encoding predicate, it belongs in InsnPredicates.

lib/Target/Mips/MipsSEISelLowering.cpp

935–936 ↗

(On Diff #35093)

!hasDSPR3() is redundant here. The predicates are cumulative so you have have DSPR3 without also having DSPR2.

948–949 ↗

(On Diff #35093)

!hasDSPR3() is redundant here. The predicates are cumulative so you have have DSPR3 without also having DSPR2.

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool hasMips32r6() const {
     return STI.getFeatureBits()[Mips::FeatureMips32r6];
   }
   bool hasMips64r6() const {
     return STI.getFeatureBits()[Mips::FeatureMips64r6];
   }
 
   bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
   bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
+  bool hasDSPR3() const { return STI.getFeatureBits()[Mips::FeatureDSPR3]; }
   bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
   bool hasCnMips() const {
     return (STI.getFeatureBits()[Mips::FeatureCnMips]);
   }
 
   bool inPicMode() {
     return IsPicEnabled;
   }

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

if (isMicroMips(STI)) {
     if (isMips32r6(STI)) {
       NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
       if (NewOpcode == -1)
         NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
     }
     else
       NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
 
+    // Check whether it is Dsp instruction.
+    if (NewOpcode == -1)
+      NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
+
     if (NewOpcode != -1) {
       if (Fixups.size() > N)
         Fixups.pop_back();
 
       Opcode = NewOpcode;
       TmpInst.setOpcode (NewOpcode);
       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
     }

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td

+//===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+class MMDSPInst<string opstr = "">
+    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
+  let InsnPredicates = [HasDSP];
+  string BaseOpcode = opstr;
+  string Arch = "mmdsp";
+  let DecoderNamespace = "MicroMips";
+}
+
+class POOL32A_3R_FMT<bits<11> op> : MMDSPInst {
+  bits<5> rd;
+  bits<5> rs;
+  bits<5> rt;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-0}  = op;
+}

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td

+//===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes MicroMips DSP instructions.
+//
+//===----------------------------------------------------------------------===//
+
+// Instruction encoding.
+class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>;
+
+// Instruction defs.
+// MIPS DSP Rev 1
+def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS;

llvm/trunk/lib/Target/Mips/Mips.td

def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
                                  FeatureNaN2008]>;
 
 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
                                       "Mips16 mode">;
 
 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
+def FeatureDSPR3
+    : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
+                       [ FeatureDSP, FeatureDSPR2 ]>;
 
 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 
 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
 
 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
                                          "microMips mode">;
 

llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td

 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
+class DspMMRel;
+
+def Dsp2MicroMips : InstrMapping {
+  let FilterClass = "DspMMRel";
+  // Instructions with the same BaseOpcode and isNVStore values form a row.
+  let RowFields = ["BaseOpcode"];
+  // Instructions with the same predicate sense form a column.
+  let ColFields = ["Arch"];
+  // The key column is the unpredicated instructions.
+  let KeyCol = ["dsp"];
+  // Value columns are PredSense=true and PredSense=false
+  let ValueCols = [["dsp"], ["mmdsp"]];
+}
+
 def HasDSP : Predicate<"Subtarget->hasDSP()">,
              AssemblerPredicate<"FeatureDSP">;
 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
                AssemblerPredicate<"FeatureDSPR2">;
+def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
+               AssemblerPredicate<"FeatureDSPR3">;
 
 // Fields.
 class Field6<bits<6> val> {
   bits<6> V = val;
 }
 
 def SPECIAL3_OPCODE : Field6<0b011111>;
 def REGIMM_OPCODE : Field6<0b000001>;
 
-class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+class DSPInst<string opstr = "">
+    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
   let Predicates = [HasDSP];
+  string BaseOpcode = opstr;
+  string Arch = "dsp";
 }
 
 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
                 InstrItinClass itin = IIPseudo>:
   MipsPseudo<outs, ins, pattern, itin> {
   let Predicates = [HasDSP];
 }
 

llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
                                       NoItinerary>;
 
 // Pseudos.
 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
                                                 NoItinerary>, Uses<[DSPPos]>;
 
 // Instruction defs.
 // MIPS DSP Rev 1
-def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
+def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 
 // Micromips r6
 include "MicroMips32r6InstrFormats.td"
 include "MicroMips32r6InstrInfo.td"
 
 // Micromips64 r6
 include "MicroMips64r6InstrFormats.td"
 include "MicroMips64r6InstrInfo.td"
+
+// Micromips DSP
+include "MicroMipsDSPInstrFormats.td"
+include "MicroMipsDSPInstrInfo.td"

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
   bool InMips16HardFloat;
 
   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
   bool PreviousInMips16Mode;
 
   // InMicroMips -- can process MicroMips instructions
   bool InMicroMipsMode;
 
-  // HasDSP, HasDSPR2 -- supports DSP ASE.
-  bool HasDSP, HasDSPR2;
+  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
+  bool HasDSP, HasDSPR2, HasDSPR3;
 
   // Allow mixed Mips16 and Mips32 in one source file
   bool AllowMixed16_32;
 
   // Optimize for space by compiling all functions as Mips 16 unless
   // it needs floating point. Functions needing floating point are
   // compiled as Mips32
   bool Os16;
public:
   bool inMips16HardFloat() const {
     return inMips16Mode() && InMips16HardFloat;
   }
   bool inMicroMipsMode() const { return InMicroMipsMode; }
   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
   bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
   bool hasDSP() const { return HasDSP; }
   bool hasDSPR2() const { return HasDSPR2; }
+  bool hasDSPR3() const { return HasDSPR3; }
   bool hasMSA() const { return HasMSA; }
   bool hasEVA() const { return HasEVA; }
   bool useSmallSection() const { return UseSmallSection; }
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }
 
   bool useSoftFloat() const { return IsSoftFloat; }
 

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
                              const MipsTargetMachine &TM)
     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
-      HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
-      HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
+      HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
+      Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM),
       TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
       TLInfo(MipsTargetLowering::create(TM, *this)) {
 
   PreviousInMips16Mode = InMips16Mode;
 

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips  -mattr=+dsp | FileCheck %s
+
+0x00 0xa4 0x18 0xcd # CHECK: addu.qb $3, $4, $5
+

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
+
+  .set noat
+  addu.qb $3, $4, $5           # CHECK: addu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xcd]
+