[DAGCombine] Truncate BUILD_VECTOR operators if necessary when constant folding vectors

[sbaranga]

Summary

The BUILD_VECTOR node will truncate its operators to match the
type. We need to take this into account when constant folding -
we need to perform a truncation before constant folding the elements.
This is because the upper bits can change the result, depending on
the operation type (for example this is the case for min/max).

This change also adds a regression test.

[jmolloy]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

13354

I'd prefer to see this as ANY_EXTEND, as that more precisely describes that the upper bits are known to be undefined.

But shouldn't this only happen if we're in the post-legalize stage?

[sbaranga]

Use ANY_EXTEND instead of ZERO_EXTEND and only do so after legalization.

[jmolloy]

This now LGTM, Thanks.

[sbaranga]

Thanks, committed in r247265.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
           N->getOpcode() == ISD::FDIV) {
         if (isNullConstant(RHSOp) || (RHSOp.getOpcode() == ISD::ConstantFP &&
              cast<ConstantFPSDNode>(RHSOp.getNode())->isZero()))
           break;
       }
 
       EVT VT = LHSOp.getValueType();
       EVT RVT = RHSOp.getValueType();
-      if (RVT != VT) {
-        // Integer BUILD_VECTOR operands may have types larger than the element
-        // size (e.g., when the element type is not legal).  Prior to type
-        // legalization, the types may not match between the two BUILD_VECTORS.
-        // Truncate one of the operands to make them match.
-        if (RVT.getSizeInBits() > VT.getSizeInBits()) {
-          RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
-        } else {
-          LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
-          VT = RVT;
-        }
+      EVT ST = VT;
+
+      if (RVT.getSizeInBits() < VT.getSizeInBits())
+        ST = RVT;
+
+      // Truncate the operands to make them match.
+      if (VT.getSizeInBits() != LHS.getValueType().getScalarSizeInBits()) {
+        EVT ScalarT = LHS.getValueType().getScalarType();
+        LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), ScalarT, LHSOp);
+        VT = LHSOp.getValueType();
+      }
+      if (RVT.getSizeInBits() != RHS.getValueType().getScalarSizeInBits()) {
+        EVT ScalarT = RHS.getValueType().getScalarType();
+        RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), ScalarT, RHSOp);
+        RVT = RHSOp.getValueType();
       }
+
       SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
                                    LHSOp, RHSOp);
+
+      // We need the resulting constant to be legal if we are in a phase after
+      // legalization, so zero extend to the smallest operand type if required.
+      if (ST != VT && Level != BeforeLegalizeTypes)
+        FoldOp = DAG.getNode(ISD::ANY_EXTEND, SDLoc(LHS), ST, FoldOp);
+
       if (FoldOp.getOpcode() != ISD::UNDEF &&
           FoldOp.getOpcode() != ISD::Constant &&
           FoldOp.getOpcode() != ISD::ConstantFP)
         break;
       Ops.push_back(FoldOp);
       AddToWorklist(FoldOp.getNode());
     }
 

test/CodeGen/AArch64/aarch64-smax-constantfold.ll

+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
+
+; Function Attrs: nounwind readnone
+declare <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16>, <4 x i16>)
+
+; CHECK-LABEL: test
+define <4 x i16> @test() {
+entry:
+; CHECK: movi d{{[0-9]+}}, #0000000000000000
+  %0 = tail call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> zeroinitializer)
+  ret <4 x i16> %0
+}