[WebAssembly] Support running without a register allocator in the default CodeGen passes

[sunfish]

Summary

WebAssembly doesn't currently use a register allocator, but it does need PHI lowering and other passes. This pass adds support to the default TargetPassConfig::addFastRegAlloc and TargetPassConfig::addOptimizedRegAlloc for detecting when a target has requested no register allocation pass.

This allows the removal of WebAssembly's custom implementations of addFastRegAlloc and addOptimizedRegAlloc.

[jfb]

Are there other virtual ISAs that would benefit from this?

Otherwise lgtm.

[sunfish]

NVPTX could theoretically benefit as well, though I didn't update it because its pass list is currently slightly different.

llvm/trunk/lib/CodeGen/Passes.cpp

 }
 
 /// Add the minimum set of target-independent passes that are required for
 /// register allocation. No coalescing or scheduling.
 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
   addPass(&PHIEliminationID, false);
   addPass(&TwoAddressInstructionPassID, false);
 
+  if (RegAllocPass)
     addPass(RegAllocPass);
 }
 
 /// Add standard target-independent passes that are tightly coupled with
 /// optimized register allocation, including coalescing, machine instruction
 /// scheduling, and register allocation itself.
 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
   addPass(&ProcessImplicitDefsID, false);
 
if (EarlyLiveIntervals)
     addPass(&LiveIntervalsID, false);
 
   addPass(&TwoAddressInstructionPassID, false);
   addPass(&RegisterCoalescerID);
 
   // PreRA instruction scheduling.
   addPass(&MachineSchedulerID);
 
+  if (RegAllocPass) {
     // Add the selected register allocation pass.
     addPass(RegAllocPass);
 
     // Allow targets to change the register assignments before rewriting.
     addPreRewrite();
 
     // Finally rewrite virtual registers.
     addPass(&VirtRegRewriterID);
 
     // Perform stack slot coloring and post-ra machine LICM.
     //
     // FIXME: Re-enable coloring with register when it's capable of adding
     // kill markers.
     addPass(&StackSlotColoringID);
 
     // Run post-ra machine LICM to hoist reloads / remats.
     //
     // FIXME: can this move into MachineLateOptimization?
     addPass(&PostRAMachineLICMID);
   }
+}
 
 //===---------------------------------------------------------------------===//
 /// Post RegAlloc Pass Configuration
 //===---------------------------------------------------------------------===//
 
 /// Add passes that optimize machine instructions after register allocation.
 void TargetPassConfig::addMachineLateOptimization() {
   // Branch folding must be run after regalloc and prolog/epilog insertion.

llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

public:
   WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 
   WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
     return getTM<WebAssemblyTargetMachine>();
   }
 
   FunctionPass *createTargetRegisterAllocator(bool) override;
-  void addFastRegAlloc(FunctionPass *RegAllocPass) override;
-  void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
 
   void addIRPasses() override;
   bool addPreISel() override;
   bool addInstSelector() override;
   bool addILPOpts() override;
   void addPreRegAlloc() override;
-  void addRegAllocPasses(bool Optimized);
   void addPostRegAlloc() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
 };
 } // end anonymous namespace
 
 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](Function &F) {
     return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
   });
 }
 
 TargetPassConfig *
 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new WebAssemblyPassConfig(this, PM);
 }
 
 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
   return nullptr; // No reg alloc
 }
 
-void WebAssemblyPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
-  assert(!RegAllocPass && "WebAssembly uses no regalloc!");
-  addRegAllocPasses(false);
-}
-
-void WebAssemblyPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
-  assert(!RegAllocPass && "WebAssembly uses no regalloc!");
-  addRegAllocPasses(true);
-}
-
 //===----------------------------------------------------------------------===//
 // The following functions are called from lib/CodeGen/Passes.cpp to modify
 // the CodeGen pass sequence.
 //===----------------------------------------------------------------------===//
 
 void WebAssemblyPassConfig::addIRPasses() {
   // FIXME: the default for this option is currently POSIX, whereas
   // WebAssembly's MVP should default to Single.
addPass(
       createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
   return false;
 }
 
 bool WebAssemblyPassConfig::addILPOpts() { return true; }
 
 void WebAssemblyPassConfig::addPreRegAlloc() {}
 
-void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
-  // This is list is derived from the regalloc pass list used in
-  // addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
-  // don't run the actual register allocator, but we do run the passes which
-  // lower SSA form, so after these passes are complete, we have non-SSA
-  // virtual registers.
-
-  if (Optimized) {
-    addPass(&ProcessImplicitDefsID);
-    addPass(&LiveVariablesID);
-    addPass(&MachineLoopInfoID);
-  }
-
-  addPass(&PHIEliminationID);
-  addPass(&TwoAddressInstructionPassID, false);
-
-  if (Optimized) {
-    addPass(&RegisterCoalescerID);
-    addPass(&MachineSchedulerID);
-  }
-}
-
 void WebAssemblyPassConfig::addPostRegAlloc() {
   // FIXME: the following passes dislike virtual registers. Disable them for now
   //        so that basic tests can pass. Future patches will remedy this.
   //
   // Fails with: Regalloc must assign all vregs.
   disablePass(&PrologEpilogCodeInserterID);
   // Fails with: should be run after register allocation.
   disablePass(&MachineCopyPropagationID);
 }
 
 void WebAssemblyPassConfig::addPreSched2() {}
 
 void WebAssemblyPassConfig::addPreEmitPass() {}