x32. Fixes jmp %reg in x32

[jpp]

Summary

x32 has 32-bit pointers; x86-64 can't jmp %r32. This patch addresses this issue by explicitly zero-extending brind's target to 64-bits.

[dschuff]

test/CodeGen/X86/x32-indirectbr.ll

21 ↗

(On Diff #32441)

%{{e|r}}
if you are checking for a movl, then %rXX shouldn't be allowed, should it?

[jpp]

test/CodeGen/X86/x32-indirectbr.ll

21 ↗

(On Diff #32441)

They are, if you are using the new registers( r8d-15d). The regexp could potentially be improved.

[jfb]

Adding Pavel, if Intel is still interested in moving x32 forward :-)

[jfb]

lib/Target/X86/X86ISelDAGToDAG.cpp

2281 ↗

(On Diff #32441)

Could you comment on why not NaCl? Maybe restyle to be more readable:

case ISD::BRIND: {
  if (Subtarget->isTargetNaCl())
    // Not NaCl because...
    break;
  if (Subtarget->isTarget64BitILP32()) {
    // ...
  }
  break;

test/CodeGen/X86/x32-indirectbr.ll

7 ↗

(On Diff #32441)

It seems like test2 relies on switch lowering's specific implementation? Is this tested here because it's generated through a different code path than indirectbr? I'd like to make sure that the tests isn't brittle if e.g. fast-isel changes, while still making sure you have proper test coverage.

9 ↗

(On Diff #32441)

CHECK-LABEL

22 ↗

(On Diff #32441)

CHECK-NEXT for this line.

24 ↗

(On Diff #32441)

CHECK-LABEL

56 ↗

(On Diff #32441)

CHECK-NEXT

[dschuff]

test/CodeGen/X86/x32-indirectbr.ll

21 ↗

(On Diff #32441)

Oh ok, I misunderstood. and the regex is explicitly trying to throw away the d for REG. It makes sense, but probably worth a comment saying that the test is checking for a 32-bit mov followed by a jump through the 64-bit version of the same register.

[jfb]

lgtm

llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
   if (Node->isMachineOpcode()) {
     DEBUG(dbgs() << "== ";  Node->dump(CurDAG); dbgs() << '\n');
     Node->setNodeId(-1);
     return nullptr;   // Already selected.
   }
 
   switch (Opcode) {
   default: break;
+  case ISD::BRIND: {
+    if (Subtarget->isTargetNaCl())
+      // NaCl has its own pass where jmp %r32 are converted to jmp %r64. We
+      // leave the instruction alone.
+      break;
+    if (Subtarget->isTarget64BitILP32()) {
+      // Converts a 32-bit register to a 64-bit, zero-extended version of
+      // it. This is needed because x86-64 can do many things, but jmp %r32
+      // ain't one of them.
+      const SDValue &Target = Node->getOperand(1);
+      assert(Target.getSimpleValueType() == llvm::MVT::i32);
+      SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, EVT(MVT::i64));
+      SDValue Brind = CurDAG->getNode(ISD::BRIND, dl, MVT::Other,
+                                      Node->getOperand(0), ZextTarget);
+      ReplaceUses(SDValue(Node, 0), Brind);
+      SelectCode(ZextTarget.getNode());
+      SelectCode(Brind.getNode());
+      return nullptr;
+    }
+    break;
+  }
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {
     default: break;
     case Intrinsic::x86_avx2_gather_d_pd:
     case Intrinsic::x86_avx2_gather_d_pd_256:
     case Intrinsic::x86_avx2_gather_q_pd:
     case Intrinsic::x86_avx2_gather_q_pd_256:

llvm/trunk/test/CodeGen/X86/x32-indirectbr.ll

+; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic -fast-isel | FileCheck %s
+; Bug 22859
+;
+; x32 pointers are 32-bits wide. x86-64 indirect branches use the full 64-bit
+; registers. Therefore, x32 CodeGen needs to zero extend indirectbr's target to
+; 64-bit.
+
+define i8 @test1() nounwind ssp {
+entry:
+  %0 = select i1 undef,                           ; <i8*> [#uses=1]
+              i8* blockaddress(@test1, %bb),
+              i8* blockaddress(@test1, %bb6)
+  indirectbr i8* %0, [label %bb, label %bb6]
+bb:                                               ; preds = %entry
+  ret i8 1
+
+bb6:                                              ; preds = %entry
+  ret i8 2
+}
+; CHECK-LABEL: @test1
+; We are looking for a movl ???, %r32 followed by a 64-bit jmp through the
+; same register.
+; CHECK: movl {{.*}}, %{{e|r}}[[REG:.[^d]*]]{{d?}}
+; CHECK-NEXT: jmpq *%r[[REG]]
+