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Differential D11631

[mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
ClosedPublic

Authored by hvarga on Jul 30 2015, 12:12 AM.

Details

Reviewers
dsanders
zbuljan
zoran.jovanovic
Commits
rL250377: [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions
Summary

The patch implements microMIPS LWLE, LWRE, SWLE and SWRE instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

hvarga updated this revision to Diff 31000.Jul 30 2015, 12:12 AM
hvarga retitled this revision from to [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions.
hvarga updated this object.
hvarga added reviewers: zoran.jovanovic, zbuljan, dsanders.
hvarga added subscribers: petarj, llvm-commits.
dsanders accepted this revision.Sep 14 2015, 7:13 AM
dsanders edited edge metadata.

LGTM with some nits

lib/Target/Mips/Disassembler/MipsDisassembler.cpp
288–290 ↗(On Diff #31000)

Indentation

lib/Target/Mips/MicroMipsInstrFormats.td
405 ↗(On Diff #31000)

Naming convention: Should begin with POOL32C_

407 ↗(On Diff #31000)

Assign to 'base' and 'offset' to make special encoding self documenting

lib/Target/Mips/MicroMipsInstrInfo.td
717–726 ↗(On Diff #31000)

Indentation

This revision is now accepted and ready to land.Sep 14 2015, 7:13 AM
Closed by commit rL250377: [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructions (authored by hvarga). · Explain WhyOct 15 2015, 12:25 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
16 lines
10 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
4 lines
4 lines
Mips/
12 lines
mips32r6/
1 line

Diff 37450

llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Linesclass LWL_FM_MM<bits<4> funct> {
let Inst{31-26} = 0x18; let Inst{31-26} = 0x18;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16}; let Inst{20-16} = addr{20-16};
let Inst{15-12} = funct; let Inst{15-12} = funct;
let Inst{11-0} = addr{11-0}; let Inst{11-0} = addr{11-0};
} }
class POOL32C_STEVA_LDEVA_FM_MM<bits<4> type, bits<3> funct> {
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
bits<9> offset = addr{8-0};
bits<32> Inst;
let Inst{31-26} = 0x18;
let Inst{25-21} = rt;
let Inst{20-16} = base;
let Inst{15-12} = type;
let Inst{11-9} = funct;
let Inst{8-0} = offset;
}
class CMov_F_I_FM_MM<bits<7> func> : MMArch { class CMov_F_I_FM_MM<bits<7> func> : MMArch {
bits<5> rd; bits<5> rd;
bits<5> rs; bits<5> rs;
bits<3> fcc; bits<3> fcc;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x15; let Inst{31-26} = 0x15;
▲ Show 20 Lines • Show All 564 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 745 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>, def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x0>; LWL_FM_MM<0x0>;
def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>, def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x1>; LWL_FM_MM<0x1>;
def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>, def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x8>; LWL_FM_MM<0x8>;
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
LWL_FM_MM<0x9>; LWL_FM_MM<0x9>;
let DecoderMethod = "DecodeMemMMImm9" in {
def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>,
POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>,
POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>,
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>,
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
}
/// Load and Store Instructions - multiple /// Load and Store Instructions - multiple
def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>;
def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>; def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>;
def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>; def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>;
def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>; def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>;
/// Load and Store Pair Instructions /// Load and Store Pair Instructions
▲ Show 20 Lines • Show All 237 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
0x82 0x60 0x08 0x62 # CHECK: lhue $4, 8($2) 0x82 0x60 0x08 0x62 # CHECK: lhue $4, 8($2)
0x82 0x60 0x08 0x68 # CHECK: lbe $4, 8($2) 0x82 0x60 0x08 0x68 # CHECK: lbe $4, 8($2)
0x82 0x60 0x08 0x60 # CHECK: lbue $4, 8($2) 0x82 0x60 0x08 0x60 # CHECK: lbue $4, 8($2)
0x82 0x60 0x08 0x6a # CHECK: lhe $4, 8($2) 0x82 0x60 0x08 0x6a # CHECK: lhe $4, 8($2)
0x82 0x60 0x08 0x6e # CHECK: lwe $4, 8($2) 0x82 0x60 0x08 0x6e # CHECK: lwe $4, 8($2)
0xa4 0x60 0x08 0xa8 # CHECK: sbe $5, 8($4) 0xa4 0x60 0x08 0xa8 # CHECK: sbe $5, 8($4)
0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4) 0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4) 0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3)
0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3)
0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3)
0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2) 0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
0x60 0x82 0x68 0x08 # CHECK: lbe $4, 8($2) 0x60 0x82 0x68 0x08 # CHECK: lbe $4, 8($2)
0x60 0x82 0x60 0x08 # CHECK: lbue $4, 8($2) 0x60 0x82 0x60 0x08 # CHECK: lbue $4, 8($2)
0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2) 0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
0x60 0x82 0x6e 0x08 # CHECK: lwe $4, 8($2) 0x60 0x82 0x6e 0x08 # CHECK: lwe $4, 8($2)
0x60 0xa4 0xa8 0x08 # CHECK: sbe $5, 8($4) 0x60 0xa4 0xa8 0x08 # CHECK: sbe $5, 8($4)
0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4) 0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4) 0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3)
0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3)
0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3)
0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)

llvm/trunk/test/MC/Mips/micromips-control-instructions.s

Show All 36 Lines
# CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93] # CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93]
# CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03] # CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03]
# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4] # CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4]
# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6] # CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6]
# CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09] # CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2]
# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0]
# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66]
# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64]
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# Big endian # Big endian
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c] # CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
# CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c] # CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
# CHECK-EB: .set push # CHECK-EB: .set push
# CHECK-EB: .set mips32r2 # CHECK-EB: .set mips32r2
# CHECK-EB: rdhwr $5, $29 # CHECK-EB: rdhwr $5, $29
Show All 20 Lines
# CHECK-EB: wait 17 # encoding: [0x00,0x11,0x93,0x7c] # CHECK-EB: wait 17 # encoding: [0x00,0x11,0x93,0x7c]
# CHECK-EB: tlbp # encoding: [0x00,0x00,0x03,0x7c] # CHECK-EB: tlbp # encoding: [0x00,0x00,0x03,0x7c]
# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c]
# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08] # CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08]
# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] # CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08]
# CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0] # CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05]
# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05]
# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05]
# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
sdbbp sdbbp
sdbbp 34 sdbbp 34
rdhwr $5, $29 rdhwr $5, $29
cache 1, 8($5) cache 1, 8($5)
pref 1, 8($5) pref 1, 8($5)
ssnop ssnop
ehb ehb
Show All 15 Lines# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02]
wait 17 wait 17
tlbp tlbp
tlbr tlbr
tlbwi tlbwi
tlbwr tlbwr
prefe 1, 8($5) prefe 1, 8($5)
cachee 1, 8($5) cachee 1, 8($5)
prefx 1, $3($5) prefx 1, $3($5)
swre $24, 5($3)
swle $24, 5($3)
lwre $24, 5($3)
lwle $24, 2($4)

llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s

# Instructions that are invalid # Instructions that are invalid
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: 2>%t1 # RUN: 2>%t1
# RUN: FileCheck %s < %t1 # RUN: FileCheck %s < %t1
.set noat .set noat
bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction