X86: Fixed assertion failure in 32-bit mode

[delena]

Summary

The DAG Node "SCALAR_TO_VECTOR" may be created if the type of scalar element is legal.
Added a check for scalar type before creating this node.
Added a test that fails with assertion on the current version.

[mkuper]

lib/Target/X86/X86ISelLowering.cpp

7385 ↗

(On Diff #30345)

This seems a bit odd - if getScalarValueForVectorElement() returned a non-null value, there was already a SCALAR_TO_VECTOR or a BUILD_VECTOR there. So why would forming a SCALAR_TO_VECTOR be wrong?

(I'm not saying it's not, I just don't understand why.)

[delena]

lib/Target/X86/X86ISelLowering.cpp

7385 ↗

(On Diff #30345)

The pattern here is " BITCAST(v2f64 (SCALAR_TO_VECTOR (f64 Val))) to v2i64."
So, the original "scalar_to_vector" was legal.

[mkuper]

LGTM.

lib/Target/X86/X86ISelLowering.cpp

7385 ↗

(On Diff #30345)

Ah, ok, makes sense.

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

if (i != V2Index && !Zeroable[i]) {
       break;
     }
 
   // Check for a single input from a SCALAR_TO_VECTOR node.
   // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
   // all the smarts here sunk into that routine. However, the current
   // lowering of BUILD_VECTOR makes that nearly impossible until the old
   // vector shuffle lowering is dead.
-  if (SDValue V2S = getScalarValueForVectorElement(
-          V2, Mask[V2Index] - Mask.size(), DAG)) {
+  SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
+                                               DAG);
+  if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
     // We need to zext the scalar if it is smaller than an i32.
     V2S = DAG.getBitcast(EltVT, V2S);
     if (EltVT == MVT::i8 || EltVT == MVT::i16) {
       // Using zext to expand a narrow element won't work for non-zero
       // insertions.
       if (!IsV1Zeroable)
         return SDValue();
 

llvm/trunk/test/CodeGen/X86/avx-shuffle-x86_32.ll

 ; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
 define <4 x i64> @test1(<4 x i64> %a) nounwind {
  %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  ret <4 x i64>%b
  ; CHECK-LABEL: test1:
  ; CHECK-NOT: vinsertf128
  }
+
+define <8 x i16> @test2(<4 x i16>* %v) nounwind {
+; CHECK-LABEL: test2
+; CHECK: vmovsd
+; CHECK: vmovq
+  %v9 = load <4 x i16>, <4 x i16> * %v, align 8
+  %v10 = shufflevector <4 x i16> %v9, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+  %v11 = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0, i16 0, i16 0>, <8 x i16> %v10, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i16> %v11
+}
+