[mips] Remove incorrect DebugLoc entries from prologue.

[vradosavljevic]

Summary

This was causing the prologue_end to be incorrectly positioned. This patch is based on http://reviews.llvm.org/D5209.

[vradosavljevic]

Ping.

[dsanders]

Could you explain a bit more? I'm not sure why/how the DebugLoc's are incorrect.

[vradosavljevic]

Machine instructions before Prologue/Epilogue Insertion:

BB#0: derived from LLVM BB %entry
	ADJCALLSTACKDOWN 16, %SP<imp-def,dead>, %SP<imp-use>; dbg:test.c:2:3
	%AT<def> = LUi <ga:@.str>[TF=5]; dbg:test.c:2:3
	%A0<def> = ADDiu %AT<kill>, <ga:@.str>[TF=6]; dbg:test.c:2:3
	JAL <ga:@printf>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7>, %A0<imp-use,kill>, %SP<imp-def>, %V0<imp-def>, ...; dbg:test.c:2:3
	ADJCALLSTACKUP 16, 0, %SP<imp-def,dead>, %SP<imp-use>; dbg:test.c:2:3
	SW %V0<kill>, <fi#0>, 0; mem:ST4[FixedStack0] dbg:test.c:3:1
	RetRA; dbg:test.c:3:1

Instructions in the prologue before this patch have the debug location from the first machine instruction (in this case debug location from ADJCALLSTACKDOWN 16). The first debug location is used to determine the prologue_end and because of that, it will be incorrectly positioned (in this case at the beginning of the prologue).

Machine instructions after Prologue/Epilogue Insertion before this patch:

BB#0: derived from LLVM BB %entry
	%SP<def> = ADDiu %SP, -24; dbg:test.c:2:3
	CFI_INSTRUCTION <call frame instruction>; dbg:test.c:2:3
	SW %RA<kill>, %SP, 20; mem:ST4[FixedStack1] dbg:test.c:2:3
	CFI_INSTRUCTION <call frame instruction>; dbg:test.c:2:3
	%AT<def> = LUi <ga:@.str>[TF=5]; dbg:test.c:2:3
	%A0<def> = ADDiu %AT<kill>, <ga:@.str>[TF=6]; dbg:test.c:2:3
	JAL <ga:@printf>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7>, %RA<imp-def,dead>, %A0<imp-use,kill>, %SP<imp-def>, %V0<imp-def>; dbg:test.c:2:3
	SW %V0<kill>, %SP, 16; mem:ST4[FixedStack0] dbg:test.c:3:1
	%RA<def> = LW %SP, 20; mem:LD4[FixedStack1] dbg:test.c:3:1
	%SP<def> = ADDiu %SP, 24; dbg:test.c:3:1
	RetRA; dbg:test.c:3:1

Machine instructions after Prologue/Epilogue Insertion with this patch:

BB#0: derived from LLVM BB %entry
	%SP<def> = ADDiu %SP, -24
	CFI_INSTRUCTION <call frame instruction>
	SW %RA<kill>, %SP, 20; mem:ST4[FixedStack1]
	CFI_INSTRUCTION <call frame instruction>
	%AT<def> = LUi <ga:@.str>[TF=5]; dbg:test.c:2:3
	%A0<def> = ADDiu %AT<kill>, <ga:@.str>[TF=6]; dbg:test.c:2:3
	JAL <ga:@printf>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7>, %RA<imp-def,dead>, %A0<imp-use,kill>, %SP<imp-def>, %V0<imp-def>; dbg:test.c:2:3
	SW %V0<kill>, %SP, 16; mem:ST4[FixedStack0]
	%RA<def> = LW %SP, 20; mem:LD4[FixedStack1] dbg:test.c:3:1
	%SP<def> = ADDiu %SP, 24
	RetRA; dbg:test.c:3:1

[dsanders]

Makes sense, thanks for explaining.

I've tried it on a couple simple tests and it doesn't seem to have any obvious negative effect on gdb. Function breakpoints and single instruction stepping still display line information correctly. Therefore, LGTM.

[vradosavljevic]

Updated test/DebugInfo/Mips/delay-slot.ll.

llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp

void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
   const MipsSEInstrInfo &TII =
       *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
   const MipsRegisterInfo &RegInfo =
       *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
 
   MachineBasicBlock::iterator MBBI = MBB.begin();
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
+  DebugLoc dl;
   MipsABIInfo ABI = STI.getABI();
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
   unsigned MOVE = ABI.GetGPRMoveOp();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
   unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
 

llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
 
   if (!MipsFI->globalBaseRegSet())
     return;
 
   MachineBasicBlock &MBB = MF.front();
   MachineBasicBlock::iterator I = MBB.begin();
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
   const TargetRegisterClass *RC;
   const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
   RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
 
   V0 = RegInfo.createVirtualRegister(RC);
   V1 = RegInfo.createVirtualRegister(RC);
 

llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp

 }
 
 void MipsSEInstrInfo::
 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                 unsigned SrcReg, bool isKill, int FI,
                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
                 int64_t Offset) const {
   DebugLoc DL;
-  if (I != MBB.end()) DL = I->getDebugLoc();
   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
 
   unsigned Opc = 0;
 
   if (Mips::GPR32RegClass.hasSubClassEq(RC))
     Opc = Mips::SW;
   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
     Opc = Mips::SD;
unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
   }
 }
 
 /// Adjust SP by Amount bytes.
 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const {
   MipsABIInfo ABI = Subtarget.getABI();
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
+  DebugLoc DL;
   unsigned ADDu = ABI.GetPtrAdduOp();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
 
   if (Amount == 0)
     return;
 
   if (isInt<16>(Amount))// addi sp, sp, amount
     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);

llvm/trunk/test/DebugInfo/Mips/delay-slot.ll

 ; }
 
 ; CHECK: Address            Line   Column File   ISA Discriminator Flags
 ; CHECK: ------------------ ------ ------ ------ --- ------------- -------------
 ; CHECK: 0x0000000000000000      1      0      1   0             0  is_stmt
 ; FIXME: The next address probably ought to be 0x0000000000000004 but there's
 ;        a constant initialization before the prologue's end.
 ; CHECK: 0x0000000000000008      2      0      1   0             0  is_stmt prologue_end
-; CHECK: 0x0000000000000028      3      0      1   0             0  is_stmt
-; CHECK: 0x0000000000000038      4      0      1   0             0  is_stmt
+; CHECK: 0x000000000000002c      3      0      1   0             0  is_stmt
+; CHECK: 0x000000000000003c      4      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000048      5      0      1   0             0  is_stmt
 ; CHECK: 0x0000000000000058      5      0      1   0             0  is_stmt end_sequence
 
 
 target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
 target triple = "mips--linux-gnu"
 
 ; Function Attrs: nounwind

llvm/trunk/test/DebugInfo/Mips/prologue_end.ll

+; RUN: llc -O0 -mtriple mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC
+; RUN: llc -O0 -mtriple mips-unknown-linux-gnu -relocation-model=static -disable-fp-elim < %s | FileCheck %s -check-prefix=STATIC-FP
+; RUN: llc -O0 -mtriple mips-unknown-linux-gnu -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
+; RUN: llc -O0 -mtriple mips-unknown-linux-gnu -relocation-model=pic -disable-fp-elim < %s | FileCheck %s -check-prefix=PIC-FP
+
+; Generated using clang -O0 -emit-llvm -S -target mipsel-unknown-linux -g test.c -o test.ll
+; test.c:
+;
+; void hello_world(void) {
+;   printf("Hello, World!\n");
+; }
+
+@.str = private unnamed_addr constant [15 x i8] c"Hello, World!\0A\00", align 1
+
+define void @hello_world() #0 {
+entry:
+; STATIC: addiu $sp, $sp, -{{[0-9]+}}
+; STATIC: sw  $ra, {{[0-9]+}}($sp)
+; STATIC: .loc  1 2 3 prologue_end
+; STATIC: lui $[[R0:[0-9]+]], %hi($.str)
+
+; STATIC-FP:  addiu $sp, $sp, -{{[0-9]+}}
+; STATIC-FP:  sw  $ra, {{[0-9]+}}($sp)
+; STATIC-FP:  sw  $fp, {{[0-9]+}}($sp)
+; STATIC-FP:  move  $fp, $sp
+; STATIC-FP:  .loc  1 2 3 prologue_end
+; STATIC-FP:  lui $[[R0:[0-9]+]], %hi($.str)
+
+; PIC:      lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; PIC:      addiu $[[R0]], $[[R0]], %lo(_gp_disp)
+; PIC:      addiu $sp, $sp, -{{[0-9]+}}
+; PIC:      sw  $ra, {{[0-9]+}}($sp)
+; PIC:      addu  $[[R1:[0-9]+]], $[[R0]], $25
+; PIC:      .loc  1 2 3 prologue_end
+; PIC:      lw  $[[R2:[0-9]+]], %got($.str)($[[R1]])
+
+; PIC-FP: lui $[[R0:[0-9]+]], %hi(_gp_disp)
+; PIC-FP: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
+; PIC-FP: addiu $sp, $sp, -{{[0-9]+}}
+; PIC-FP: sw  $ra, {{[0-9]+}}($sp)
+; PIC-FP: sw  $fp, {{[0-9]+}}($sp)
+; PIC-FP: move  $fp, $sp
+; PIC-FP: addu  $[[R1:[0-9]+]], $[[R0]], $25
+; PIC-FP: .loc  1 2 3 prologue_end
+; PIC-FP: lw  $[[R2:[0-9]+]], %got($.str)($[[R1]])
+
+  %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([15 x i8], [15 x i8]* @.str, i32 0, i32 0)), !dbg !10
+  ret void, !dbg !11
+}
+
+declare i32 @printf(i8*, ...)
+
+attributes #0 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8}
+!llvm.ident = !{!9}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3)
+!1 = !DIFile(filename: "test.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DISubprogram(name: "hello_world", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, function: void ()* @hello_world, variables: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{null}
+!7 = !{i32 2, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{!"clang version 3.8.0"}
+!10 = !DILocation(line: 2, column: 3, scope: !4)
+!11 = !DILocation(line: 3, column: 1, scope: !4)