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Differential D11136

[mips] Added support for the ERETNC instruction.
ClosedPublic

Authored by s.egerton on Jul 13 2015, 3:18 AM.

Details

Reviewers
dsanders
vkalintiris
Commits
rG974d4092594a: [mips] Added support for the ERETNC instruction.
rL242666: [mips] Added support for the ERETNC instruction.
Summary

This required adding the instruction predicate HasMips32r5.

Diff Detail

Repository
rL LLVM

Event Timeline

s.egerton updated this revision to Diff 29545.Jul 13 2015, 3:18 AM
s.egerton retitled this revision from to [mips] Added support for the ERETNC instruction..
s.egerton updated this object.
s.egerton added reviewers: dsanders, vkalintiris.
s.egerton added a subscriber: llvm-commits.
vkalintiris requested changes to this revision.Jul 19 2015, 2:02 PM
vkalintiris edited edge metadata.

We can re-use the classes ER_FM and ER_FT for the definition of the ERETNC instruction.

Also, I believe that we should use (or create) invalid-mips32r5.s in order to test errors for pre-R5 ISAs. Please. wait for Daniel's response on that.

lib/Target/Mips/MipsInstrFormats.td
656–664 ↗(On Diff #29545)

We can re-use the ER_FM format above by adding a boolean parameter that sets the 6th bit.

lib/Target/Mips/MipsInstrInfo.td
880–884 ↗(On Diff #29545)

We can just use ER_FT for the ERETNC definition since the classes are identical.

test/MC/Mips/mips32/valid-xfail.s
38 ↗(On Diff #29545)

@dsanders: I believe that we should place this test in invalid-mips32r5.s for pre-R5 ISAs, right?

This revision now requires changes to proceed.Jul 19 2015, 2:02 PM
dsanders edited edge metadata.Jul 20 2015, 3:11 AM

Thanks for reviewing this.

test/MC/Mips/mips32/valid-xfail.s
38 ↗(On Diff #29545)

Not quite. $isa/valid-xfail.s is for instructions that should be valid on $isa but currently xfail. $isa1/invalid-$isa2.s is for instructions that are valid on $isa1 and invalid on $isa2.

This is valid on MIPS32r5 and invalid on MIPS32 so it belongs in mips32r5/invalid-mips32{,r2,r3}.s

s.egerton updated this revision to Diff 30144.Jul 20 2015, 3:40 AM
s.egerton edited edge metadata.

Addressed reviewers comments. Also added dissambler tests.

vkalintiris accepted this revision.Jul 20 2015, 5:27 AM
vkalintiris edited edge metadata.

LGTM. I will apply this for you, since you don't have commit access yet.

This revision is now accepted and ready to land.Jul 20 2015, 5:27 AM
Closed by commit rL242666: [mips] Added support for the ERETNC instruction. (authored by vkalintiris). · Explain WhyJul 20 2015, 5:29 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
6 lines
8 lines
2 lines
test/
MC/
Disassembler/
Mips/
mips32r5/
1 line
mips32r6/
1 line
mips64r5/
1 line
mips64r6/
1 line
Mips/
mips32r5/
8 lines
8 lines
8 lines
1 line
mips32r6/
2 lines
mips64r5/
8 lines
8 lines
8 lines
1 line
mips64r6/
1 line

Diff 30151

llvm/trunk/lib/Target/Mips/MipsInstrFormats.td

Show First 20 Lines • Show All 638 Lines • ▼ Show 20 Linesclass BRK_FM<bits<6> funct> : StdArch
let Inst{15-6} = code_2; let Inst{15-6} = code_2;
let Inst{5-0} = funct; let Inst{5-0} = funct;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Exception return format <Cop0|1|0|funct> // Exception return format <Cop0|1|0|funct>
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ER_FM<bits<6> funct> : StdArch class ER_FM<bits<6> funct, bit LLBit> : StdArch
{ {
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x10; let Inst{31-26} = 0x10;
let Inst{25} = 1; let Inst{25} = 1;
let Inst{24-6} = 0; let Inst{24-7} = 0;
let Inst{6} = LLBit;
let Inst{5-0} = funct; let Inst{5-0} = funct;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> // Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class EI_FM<bits<1> sc> : StdArch class EI_FM<bits<1> sc> : StdArch
{ {
bits<32> Inst; bits<32> Inst;
bits<5> rt; bits<5> rt;
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llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

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def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
AssemblerPredicate<"FeatureMips4_32r2">; AssemblerPredicate<"FeatureMips4_32r2">;
def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
AssemblerPredicate<"FeatureMips5_32r2">; AssemblerPredicate<"FeatureMips5_32r2">;
def HasMips32 : Predicate<"Subtarget->hasMips32()">, def HasMips32 : Predicate<"Subtarget->hasMips32()">,
AssemblerPredicate<"FeatureMips32">; AssemblerPredicate<"FeatureMips32">;
def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
AssemblerPredicate<"FeatureMips32r2">; AssemblerPredicate<"FeatureMips32r2">;
def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
AssemblerPredicate<"FeatureMips32r5">;
def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
AssemblerPredicate<"FeatureMips32r6">; AssemblerPredicate<"FeatureMips32r6">;
def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
AssemblerPredicate<"!FeatureMips32r6">; AssemblerPredicate<"!FeatureMips32r6">;
def IsGP64bit : Predicate<"Subtarget->isGP64bit()">, def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
AssemblerPredicate<"FeatureGP64Bit">; AssemblerPredicate<"FeatureGP64Bit">;
def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
AssemblerPredicate<"!FeatureGP64Bit">; AssemblerPredicate<"!FeatureGP64Bit">;
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class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; } class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
class ISA_MIPS32_NOT_32R6_64R6 { class ISA_MIPS32_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
} }
class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; } class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
class ISA_MIPS32R2_NOT_32R6_64R6 { class ISA_MIPS32R2_NOT_32R6_64R6 {
list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
} }
class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; } class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
class ISA_MIPS64_NOT_64R6 { class ISA_MIPS64_NOT_64R6 {
list<Predicate> InsnPredicates = [HasMips64, NotMips64r6]; list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
} }
class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; } class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; } class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; } class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
class ISA_MICROMIPS32R6 { class ISA_MICROMIPS32R6 {
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let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>; def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
} }
def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
def TRAP : TrapBase<BREAK>; def TRAP : TrapBase<BREAK>;
def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
} }
def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2; def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
} }
def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2; def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
AdditionalPredicates = [NotInMicroMips] in { AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 671 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

Show First 20 Lines • Show All 183 Lines • ▼ Show 20 Lines return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
hasMips64r2(); hasMips64r2();
} }
bool hasMips32r3() const { bool hasMips32r3() const {
return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
hasMips64r2(); hasMips64r2();
} }
bool hasMips32r5() const { bool hasMips32r5() const {
return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
hasMips64r2(); hasMips64r5();
} }
bool hasMips32r6() const { bool hasMips32r6() const {
return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
hasMips64r6(); hasMips64r6();
} }
bool hasMips64() const { return MipsArchVersion >= Mips64; } bool hasMips64() const { return MipsArchVersion >= Mips64; }
bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
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llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

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0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7 0x46 0x07 0x30 0x39 # CHECK: c.ngle.s $f6, $f7
0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7
0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3b # CHECK: c.ngl.s $f6, $f7
0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
0x42 0x00 0x00 0x58 # CHECK: eretnc
0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7 0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7 0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18
0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14 0x46 0x20 0x73 0x04 # CHECK: sqrt.d $f12, $f14
0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14 0x46 0x20 0x73 0x05 # CHECK: abs.d $f12, $f14
0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14 0x46 0x20 0x73 0x07 # CHECK: neg.d $f12, $f14
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llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

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0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) 0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
Show All 37 Lines

llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt

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0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14
0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14 0x46 0x2e 0x60 0x39 # CHECK: c.ngle.d $f12, $f14
0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14 0x46 0x2e 0x60 0x3a # CHECK: c.seq.d $f12, $f14
0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14 0x46 0x2e 0x60 0x3b # CHECK: c.ngl.d $f12, $f14
0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14 0x46 0x2e 0x60 0x3c # CHECK: c.lt.d $f12, $f14
0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14 0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14 0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14 0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
0x42 0x00 0x00 0x58 # CHECK: eretnc
0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14 0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14 0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 # CHECK: cvt.s.w $f6, $f7
0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5) 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
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llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

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0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4
0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
0x42 0x00 0x00 0x58 # CHECK: eretnc
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12 0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, 12
0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6) 0x49 0x52 0x34 0xb7 # CHECK: lwc2 $18, -841($6)
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16) 0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32.s

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r2.s

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/mips32r5/invalid-mips32r3.s

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/mips32r5/valid.s

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesa:
div $zero,$25,$11 div $zero,$25,$11
div.d $f29,$f20,$f27 div.d $f29,$f20,$f27
div.s $f4,$f5,$f15 div.s $f4,$f5,$f15
divu $zero,$25,$15 divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
▲ Show 20 Lines • Show All 164 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips32r6/valid.s

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Linesa:
cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f]
cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f]
di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a]
divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01] mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64.s

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r2.s

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/mips64r5/invalid-mips64r3.s

# Instructions that are invalid
#
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r3 \
# RUN: 2>%t1
# RUN: FileCheck %s < %t1
.set noat
eretnc # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/mips64r5/valid.s

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Linesa:
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
eret eret
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
floor.l.d $f26,$f7 floor.l.d $f26,$f7
floor.l.s $f12,$f5 floor.l.s $f12,$f5
floor.w.d $f14,$f11 floor.w.d $f14,$f11
floor.w.s $f8,$f9 floor.w.s $f8,$f9
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
▲ Show 20 Lines • Show All 176 Lines • Show Last 20 Lines

llvm/trunk/test/MC/Mips/mips64r6/valid.s

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Linesa:
dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d] dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
dneg $2 # CHECK: dneg $2, $2 # encoding: [0x00,0x02,0x10,0x2e] dneg $2 # CHECK: dneg $2, $2 # encoding: [0x00,0x02,0x10,0x2e]
dneg $2,$3 # CHECK: dneg $2, $3 # encoding: [0x00,0x03,0x10,0x2e] dneg $2,$3 # CHECK: dneg $2, $3 # encoding: [0x00,0x03,0x10,0x2e]
dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f] dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
eretnc # CHECK: eretnc # encoding: [0x42,0x00,0x00,0x58]
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A] j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A] j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26 # CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines