WebAssembly: start instructions

[jfb]

Summary

• Add 64-bit address space feature, and threads feature.
• Rename SIMD feature to SIMD128.
• Rename generic processor to MVP, to follow design's lead.
• Add bleeding-edge 32 and 64 processors, with all features included.
• Fix a few DEBUG_TYPE to match other backends.

[sunfish]

lib/Target/WebAssembly/WebAssembly.td

26 ↗

(On Diff #28893)

Ok.

30 ↗

(On Diff #28893)

Ok.

61 ↗

(On Diff #28893)

The way similar things work on other targets is that there's one ProcessorModel which supports both 32-bit and 64-bit mode.

lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

15 ↗

(On Diff #28893)

FWIW, see
https://github.com/llvm-mirror/llvm/blob/5be64c403b49bb0d6a2b528613e813d04108b6c3/lib/Target/ARM/ARMTargetMachine.cpp#L321
for how something similar is done on ARM.

lib/Target/WebAssembly/WebAssemblyInstrInfo.td

19 ↗

(On Diff #28893)

We should add a HasAddr32 predicate too, since 64-bit mode can't use 32-bit addresses.

lib/Target/WebAssembly/WebAssemblySubtarget.h

32 ↗

(On Diff #28893)

64-bit mode is implied by TargetTriple.isArch64Bit() so we don't need a separate field here.

[jfb]

• Address sunfish's comments.

[jfb]

• Remove obsolete note.

[jfb]

@sunfish updated. I left a FIXME for the atomic IR passes, but I think we can figure it out later.

[sunfish]

lgtm

llvm/trunk/lib/Target/WebAssembly/WebAssembly.td

 //===----------------------------------------------------------------------===//
 
 include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // WebAssembly Subtarget features.
 //===----------------------------------------------------------------------===//
 
-def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true",
-                                   "Enable SIMD">;
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
+                                      "Enable 128-bit SIMD">;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "WebAssemblyRegisterInfo.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "WebAssemblyInstrInfo.td"
 
 def WebAssemblyInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // WebAssembly Processors supported.
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>;
+// Minimal Viable Product.
+def : ProcessorModel<"mvp", NoSchedModel, []>;
+
+// Latest and greatest experimental version of WebAssembly. Bugs included!
+def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
 
 //===----------------------------------------------------------------------===//
 // Target Declaration
 //===----------------------------------------------------------------------===//
 
 def WebAssembly : Target {
   let InstructionSet = WebAssemblyInstrInfo;
 }

llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp

 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "frame-info"
+#define DEBUG_TYPE "wasm-frame-info"
 
 // TODO: Implement a red zone?
 
 /// Return true if the specified function should have a dedicated frame pointer
 /// register.
 bool WebAssemblyFrameLowering::hasFP(const MachineFunction &MF) const {
   llvm_unreachable("TODO: implement hasFP");
 }

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

 // WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // WebAssembly Atomic operand code-gen constructs.
 //
 //===----------------------------------------------------------------------===//
 
+// TODO: Implement atomic instructions.
+
 //===----------------------------------------------------------------------===//
 // Atomic fences
 //===----------------------------------------------------------------------===//
 
 // TODO: add atomic fences here...
 
 //===----------------------------------------------------------------------===//
 // Atomic loads

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

 // WebAssembly Instruction definitions.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // WebAssembly Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
 
+def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
+def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
+def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
+                           AssemblerPredicate<"FeatureSIMD128", "simd128">;
+
 //===----------------------------------------------------------------------===//
 // WebAssembly-specific DAG Node Types.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // WebAssembly-specific DAG Nodes.
 //===----------------------------------------------------------------------===//
 

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // WebAssembly SIMD operand code-gen constructs.
 //
 //===----------------------------------------------------------------------===//
 
 // TODO: Implement SIMD instructions.
-// Note: use Requires<[HasSIMD]>.
+// Note: use Requires<[HasSIMD128]>.

llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h

 #include <string>
 
 #define GET_SUBTARGETINFO_HEADER
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 namespace llvm {
 
 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
-  bool HasSIMD;
+  bool HasSIMD128;
 
   /// String name of used CPU.
   std::string CPUString;
 
   /// What processor and OS we're targeting.
   Triple TargetTriple;
 
   WebAssemblyFrameLowering FrameLowering;
public:
   const WebAssemblyTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const Triple &getTargetTriple() const { return TargetTriple; }
   bool enableMachineScheduler() const override;
   bool useAA() const override { return true; }
 
   // Predicates used by WebAssemblyInstrInfo.td.
-  bool hasSIMD() const { return HasSIMD; }
+  bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
+  bool hasSIMD128() const { return HasSIMD128; }
 
   /// Parses features string setting specified subtarget options. Definition of
   /// function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 };
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp

 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyInstrInfo.h"
 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
 #include "WebAssemblySubtarget.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "subtarget"
+#define DEBUG_TYPE "wasm-subtarget"
 
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_TARGET_DESC
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 WebAssemblySubtarget &
 WebAssemblySubtarget::initializeSubtargetDependencies(StringRef FS) {
   // Determine default and user-specified characteristics
 
   if (CPUString.empty())
     CPUString = "generic";
 
   ParseSubtargetFeatures(CPUString, FS);
   return *this;
 }
 
 WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
                                            const std::string &CPU,
                                            const std::string &FS,
                                            const TargetMachine &TM)
-    : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD(true), CPUString(CPU),
-      TargetTriple(TT), FrameLowering(),
+    : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
+      CPUString(CPU), TargetTriple(TT), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(FS)),
       TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
 
 bool WebAssemblySubtarget::enableMachineScheduler() const { return true; }

llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

 #include "WebAssemblyTargetTransformInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/IR/Function.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Transforms/Scalar.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm"
 
 extern "C" void LLVMInitializeWebAssemblyTarget() {
   // Register the target.
   RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32);
   RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64);

 }
 
 //===----------------------------------------------------------------------===//
 // The following functions are called from lib/CodeGen/Passes.cpp to modify
 // the CodeGen pass sequence.
 //===----------------------------------------------------------------------===//
 
 void WebAssemblyPassConfig::addIRPasses() {
+  // FIXME: the default for this option is currently POSIX, whereas
+  // WebAssembly's MVP should default to Single.
+  if (TM->Options.ThreadModel == ThreadModel::Single)
+    addPass(createLowerAtomicPass());
+  else
     // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
     // control specifically what gets lowered.
-  addPass(createAtomicExpandPass(&getTM<WebAssemblyTargetMachine>()));
+    addPass(createAtomicExpandPass(TM));
 
   TargetPassConfig::addIRPasses();
 }
 
 bool WebAssemblyPassConfig::addPreISel() { return false; }
 
 bool WebAssemblyPassConfig::addInstSelector() {
   addPass(