[mips] MFC0, MTC0 changes, COP0 register class definition.

[sdardis]

Summary

Defined a new register class for coprocessor 0's registers.

The instruction definitions for DMTC0, DMFC0, MFC0 and MTC0 have been changed to reflect this.

[dsanders]

The change looks correct to me but the patch lacks appropriate test cases. Could you add them?

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

82–83

Tiny nit: Could you add a small comment that the FPU is COP1? This will make the ordering of the if-statements obvious.

[sdardis]

Tests for mfc0, mtc0, and double word variants in the disassembler.
Reginfo usage test for COP0.

Is there any else required?

Thanks.

[sdardis]

Apologies, last submission had a broken test.

[dsanders]

Thanks. The tests need expanding on a bit (mostly copy/paste into each ISA's test file) and the commit message needs improving (particularly the subject line) but after that it will LGTM. I'm aware you don't have commit access yet, so could you update the revision and I'll commit from there.

To elaborate on the tests that are needed: For the disassembler, the tests you've added need to be duplicated in each ISA's test (test/MC/Disassembler/Mips/$isa/valid-$isa.txt and test/MC/Disassembler/Mips/$isa/valid-$isa-el.txt for big/little endian respectively). I believe that mfc0/mtc0 also need to be included in the tests for the 64-bit ISA's since they are still valid instructions. The tests are laid out like this to make it easy to inspect the differences between the ISA's and manually check against documentation. These files should be sorted by opcode.

For the assembler, we also need to test the encoding is correct. The existing tests for this are in test/MC/Mips/*/valid.s (one for each ISA). These files are sorted alphabetically to make it easy to verify against the documentation and inspect the ISA differences using diff. Lastly, we also need to add to test/MC/Mips/$isa1/invalid-$isa2.s which tests that $isa1 rejects things that were valid for $isa2. In this case, we just need to update the existing test/MC/Mips/*/invalid-mips64.s to check that dmfc0/dmtc0 are rejected with the correct error message. If they are rejected but with the wrong error message then there are also invalid-*-xfail.txt tests that can be used.

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

84

Nit: LLVM uses '//' comments.

[sdardis]

Added tests, addressed nit.

[sdardis]

Apologies for spam attached wrong revision, this is the correct one.

[dsanders]

LGTM. I'm aware you don't have commit access yet so I'll commit this shortly.

I realize I said that disassembler tests are supposed to be sorted by opcode but it looks like they're sorted by mnemonic. You've made the correct change despite my mistake. Thanks.

[dsanders]

In the commit, I've fixed a couple issues that came up when running 'ninja check'.

• Some little endian disassembler tests failed because they had the same opcode as big endian. I've byte-swapped them.
• Two disassembler tests failed because their expectation was different for the same opcode as the other ISA's.

I also marked DMFC0 as being part of MIPS3 like the other DM[FT]C0's.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

enum RegKind {
     RegKind_MSA128 = 8,   /// MSA128[BHWD] (makes no difference which)
     RegKind_MSACtrl = 16, /// MSA control registers
     RegKind_COP2 = 32,    /// COP2
     RegKind_ACC = 64,     /// HI32DSP, LO32DSP, and ACC64DSP (depending on
                           /// context).
     RegKind_CCR = 128,    /// CCR
     RegKind_HWRegs = 256, /// HWRegs
     RegKind_COP3 = 512,   /// COP3
-
+    RegKind_COP0 = 1024,  /// COP0
     /// Potentially any (e.g. $1)
     RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
                       RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
-                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3
+                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
   };
 
 private:
   enum KindTy {
     k_Immediate,     /// An immediate (possibly involving symbol references)
     k_Memory,        /// Base + Offset Memory Address
     k_PhysRegister,  /// A physical register from the Mips namespace
     k_RegisterIndex, /// A register index in one or more RegKind.
private:
   /// Coerce the register to MSACtrl and return the real register for the
   /// current target.
   unsigned getMSACtrlReg() const {
     assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
     unsigned ClassID = Mips::MSACtrlRegClassID;
     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
   }
 
+  /// Coerce the register to COP0 and return the real register for the
+  /// current target.
+  unsigned getCOP0Reg() const {
+    assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
+    unsigned ClassID = Mips::COP0RegClassID;
+    return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
+  }
+
   /// Coerce the register to COP2 and return the real register for the
   /// current target.
   unsigned getCOP2Reg() const {
     assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
     unsigned ClassID = Mips::COP2RegClassID;
     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
   }
 
void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::createReg(getMSA128Reg()));
   }
 
   void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
   }
 
+  void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
+  }
+
   void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
   }
 
   void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(getCOP3Reg()));
if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
       return false;
     if (!AsmParser.hasEightFccRegisters())
       return RegIdx.Index == 0;
     return RegIdx.Index <= 7;
   }
   bool isACCAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
   }
+  bool isCOP0AsmReg() const {
+    return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
+  }
   bool isCOP2AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
   }
   bool isCOP3AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
   }
   bool isMSA128AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
                                                uint64_t Address,
                                                const void *Decoder);
 
 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
                                                unsigned RegNo,
                                                uint64_t Address,
                                                const void *Decoder);
 
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
+                                            unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder);
+
 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
                                             unsigned RegNo,
                                             uint64_t Address,
                                             const void *Decoder);
 
 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
                                        unsigned Offset,
                                        uint64_t Address,
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
   if (RegNo > 7)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
+                                            unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo > 31)
+    return MCDisassembler::Fail;
+
+  unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
                                             unsigned RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);

lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp

for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid();
     unsigned CurrentSubReg = *SubRegIt;
 
     unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg);
     Value |= 1 << EncVal;
 
     if (GPR32RegClass->contains(CurrentSubReg) ||
         GPR64RegClass->contains(CurrentSubReg))
       ri_gprmask |= Value;
+    else if (COP0RegClass->contains(CurrentSubReg))
+      ri_cprmask[0] |= Value;
+    // MIPS COP1 is the FPU.
     else if (FGR32RegClass->contains(CurrentSubReg) ||
              FGR64RegClass->contains(CurrentSubReg) ||
              AFGR64RegClass->contains(CurrentSubReg) ||
              MSA128BRegClass->contains(CurrentSubReg))
       ri_cprmask[1] |= Value;
     else if (COP2RegClass->contains(CurrentSubReg))
       ri_cprmask[2] |= Value;
     else if (COP3RegClass->contains(CurrentSubReg))
       ri_cprmask[3] |= Value;
   }
 }

lib/Target/Mips/Mips64InstrInfo.td

 def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>;
 def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>;
 }
 
 }
 
 /// Move between CPU and coprocessor registers
 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
-def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
-def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
-def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
-def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
+def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>;
+def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
+def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
+def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
 }
 
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//
 
 // extended loads
 def : MipsPat<(i64 (extloadi1  addr:$src)), (LB64 addr:$src)>;

 def : MipsInstAlias<"dsra $rd, $rt, $rs",
                     (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
                     (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
 
 // Two operand (implicit 0 selector) versions:
-def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
+def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
 
 let Predicates = [HasMips64, HasCnMips] in {
 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
 def : MipsInstAlias<"syncs",      (SYNC 0x6), 0>;
 def : MipsInstAlias<"syncw",      (SYNC 0x4), 0>;
 def : MipsInstAlias<"syncws",     (SYNC 0x5), 0>;
 }
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
   MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
                      !strconcat(instr_asm, "\t$rt, $imm64")> ;
 def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;

lib/Target/Mips/MipsInstrInfo.td

 class SCBase<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
   let DecoderMethod = "DecodeMem";
   let mayStore = 1;
   let Constraints = "$rt = $dst";
 }
 
-class MFC3OP<string asmstr, RegisterOperand RO> :
-  InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
+class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+  InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
+         !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
+
+class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
+  InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
          !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
 
 class TrapBase<Instruction RealInst>
   : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
     PseudoInstExpansion<(RealInst 0, 0)> {
   let isBarrier = 1;
   let isTerminator = 1;
   let isCodeGenOnly = 1;
def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
                                0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
 
 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
 
 /// Move Control Registers From/To CPU Registers
-def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
-def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
-def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
-def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
+def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
+def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
+def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
+def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
 
 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
                                       FrmOther, asmstr>;
 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
 
 // JR_HB and JALR_HB are defined here using the new style naming
def : MipsInstAlias<"xor $rs, $rt, $imm",
                     (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : MipsInstAlias<"xor $rs, $imm",
                     (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $rt, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
-def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
-def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
+def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
+def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
 }
 def : MipsInstAlias<"bnez $rs,$offset",
                     (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"bnezl $rs,$offset",
                     (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 def : MipsInstAlias<"beqz $rs,$offset",

lib/Target/Mips/MipsOptionRecord.h

MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context)
 
     const MCRegisterInfo *TRI = Context.getRegisterInfo();
     GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
     GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
     FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
     FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
     AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
     MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
+    COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
     COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
     COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
   }
   ~MipsRegInfoRecord() override {}
 
   void EmitMipsOptionRecord() override;
   void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
 
 private:
   MipsELFStreamer *Streamer;
   MCContext &Context;
   const MCRegisterClass *GPR32RegClass;
   const MCRegisterClass *GPR64RegClass;
   const MCRegisterClass *FGR32RegClass;
   const MCRegisterClass *FGR64RegClass;
   const MCRegisterClass *AFGR64RegClass;
   const MCRegisterClass *MSA128BRegClass;
+  const MCRegisterClass *COP0RegClass;
   const MCRegisterClass *COP2RegClass;
   const MCRegisterClass *COP3RegClass;
   uint32_t ri_gprmask;
   uint32_t ri_cprmask[4];
   int64_t ri_gp_value;
 };
 } // namespace llvm
 #endif

lib/Target/Mips/MipsRegisterInfo.td

let Namespace = "Mips" in {
   // FP control registers.
   foreach I = 0-31 in
   def FCR#I : MipsReg<#I, ""#I>;
 
   // FP condition code registers.
   foreach I = 0-7 in
   def FCC#I : MipsReg<#I, "fcc"#I>;
 
+  // COP0 registers.
+  foreach I = 0-31 in
+  def COP0#I : MipsReg<#I, ""#I>;
+
   // COP2 registers.
   foreach I = 0-31 in
   def COP2#I : MipsReg<#I, ""#I>;
 
   // COP3 registers.
   foreach I = 0-31 in
   def COP3#I : MipsReg<#I, ""#I>;
 

 }
 
 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
   let Size = 64;
 }
 
 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
 
+// Coprocessor 0 registers.
+def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,
+           Unallocatable;
+
 // Coprocessor 2 registers.
 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
            Unallocatable;
 
 // Coprocessor 3 registers.
 def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
            Unallocatable;
 

 def CCROpnd : RegisterOperand<CCR> {
   let ParserMatchClass = CCRAsmOperand;
 }
 
 def HWRegsAsmOperand : MipsAsmRegOperand {
   let Name = "HWRegsAsmReg";
 }
 
+def COP0AsmOperand : MipsAsmRegOperand {
+  let Name = "COP0AsmReg";
+}
+
 def COP2AsmOperand : MipsAsmRegOperand {
   let Name = "COP2AsmReg";
 }
 
 def COP3AsmOperand : MipsAsmRegOperand {
   let Name = "COP3AsmReg";
 }
 

 def HI32DSPOpnd : RegisterOperand<HI32DSP> {
   let ParserMatchClass = HI32DSPAsmOperand;
 }
 
 def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
   let ParserMatchClass = ACC64DSPAsmOperand;
 }
 
+def COP0Opnd : RegisterOperand<COP0> {
+  let ParserMatchClass = COP0AsmOperand;
+}
+
 def COP2Opnd : RegisterOperand<COP2> {
   let ParserMatchClass = COP2AsmOperand;
 }
 
 def COP3Opnd : RegisterOperand<COP3> {
   let ParserMatchClass = COP3AsmOperand;
 }
 

test/MC/Disassembler/Mips/mips32.txt

 0x98 0xa3 0x00 0x10
 
 # CHECK: madd   $6,  $7
 0x70 0xc7 0x00 0x00
 
 # CHECK: maddu  $6,  $7
 0x70 0xc7 0x00 0x01
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x44 0x06 0x38 0x00
 
 # CHECK: mfhi  $5
 0x00 0x00 0x28 0x10
 
 # CHECK: mflo  $5
 0x00 0x00 0x28 0x12

 0x46,0x1d,0x11,0x11
 
 # CHECK: msub   $6,  $7
 0x70 0xc7 0x00 0x04
 
 # CHECK: msubu  $6,  $7
 0x70 0xc7 0x00 0x05
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x44 0x86 0x38 0x00
 
 # CHECK: mthi   $7
 0x00 0xe0 0x00 0x11
 
 # CHECK: mtlo   $7
 0x00 0xe0 0x00 0x13

test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt

 0xc6 0x23 0xe9 0xc0 # CHECK: ll $9, 9158($7)
 0x67 0x45 0x06 0x3c # CHECK: lui $6, 17767
 0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
 0x19 0x00 0x65 0x00 # CHECK: multu $3, $5

test/MC/Disassembler/Mips/mips32/valid-mips32.txt

 0xc0 0xe9 0x23 0xc6 # CHECK: ll $9, 9158($7)
 0x3c 0x06 0x45 0x67 # CHECK: lui $6, 17767
 0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
 0x00 0x65 0x00 0x19 # CHECK: multu $3, $5

test/MC/Disassembler/Mips/mips32_le.txt

 0x10 0x00 0xa3 0x98
 
 # CHECK: madd   $6,  $7
 0x00 0x00 0xc7 0x70
 
 # CHECK: maddu  $6,  $7
 0x01 0x00 0xc7 0x70
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x00 0x38 0x06 0x44
 
 # CHECK: mfhi  $5
 0x10 0x28 0x00 0x00
 
 # CHECK: mflo  $5
 0x12 0x28 0x00 0x00

 0x11,0x11,0x1d,0x46
 
 # CHECK: msub   $6,  $7
 0x04 0x00 0xc7 0x70
 
 # CHECK: msubu  $6,  $7
 0x05 0x00 0xc7 0x70
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x00 0x38 0x86 0x44
 
 # CHECK: mthi   $7
 0x11 0x00 0xe0 0x00
 
 # CHECK: mtlo   $7
 0x13 0x00 0xe0 0x00

test/MC/Disassembler/Mips/mips32r2.txt

 0x4d 0xcc 0x05 0x00
 
 # CHECK: madd   $6,  $7
 0x70 0xc7 0x00 0x00
 
 # CHECK: maddu  $6,  $7
 0x70 0xc7 0x00 0x01
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x44 0x06 0x38 0x00
 
 # CHECK: mfhi  $5
 0x00 0x00 0x28 0x10
 
 # CHECK: mflo  $5
 0x00 0x00 0x28 0x12
 
 # CHECK: mov.d $f6, $f8
 0x46 0x20 0x41 0x86
 
 # CHECK: mov.s $f6, $f7
 0x46 0x00 0x39 0x86
 
 # CHECK: msub   $6,  $7
 0x70 0xc7 0x00 0x04
 
 # CHECK: msubu  $6,  $7
 0x70 0xc7 0x00 0x05
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x44 0x86 0x38 0x00
 
 # CHECK: mthi   $7
 0x00 0xe0 0x00 0x11
 
 # CHECK: mtlo   $7
 0x00 0xe0 0x00 0x13

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt

 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $16, 4
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt

 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $16, 4
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips32r2_le.txt

 0x00 0x05 0xcc 0x4d
 
 # CHECK: madd   $6,  $7
 0x00 0x00 0xc7 0x70
 
 # CHECK: maddu  $6,  $7
 0x01 0x00 0xc7 0x70
 
+# CHECK: mfc0 $8, $16, 4
+0x40 0x08 0x80 0x04
+
 # CHECK: mfc1   $6, $f7
 0x00 0x38 0x06 0x44
 
 # CHECK: mfhi  $5
 0x10 0x28 0x00 0x00
 
 # CHECK: mflo  $5
 0x12 0x28 0x00 0x00
 
 # CHECK: mov.d $f6, $f8
 0x86 0x41 0x20 0x46
 
 # CHECK: mov.s $f6, $f7
 0x86 0x39 0x00 0x46
 
 # CHECK: msub   $6,  $7
 0x04 0x00 0xc7 0x70
 
 # CHECK: msubu  $6,  $7
 0x05 0x00 0xc7 0x70
 
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: mtc1   $6, $f7
 0x00 0x38 0x86 0x44
 
 # CHECK: mthi   $7
 0x11 0x00 0xe0 0x00
 
 # CHECK: mtlo   $7
 0x13 0x00 0xe0 0x00

test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt

 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt

 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt

 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0xa1 0xd4 0x94 0x4e # CHECK: madd.d $f18, $f20, $f26, $f20
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0xa9 0xf2 0x52 0x4c # CHECK: msub.d $f10, $f2, $f30, $f18
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt

 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips32r6.txt

 0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
 # 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256
 # 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256
 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
+0x40 0x08 0x80 0x08 # CHECK: mfc0 $8, $16, 4
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
 0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4
 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

 0x00 0x60 0x60 0x41 # CHECK: di
 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4
 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4
 0x20 0x60 0x6e 0x41 # CHECK: ei $14
 0x20 0x60 0x60 0x41 # CHECK: ei
 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 3
 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
 0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
 0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
 0x98 0x18 0x04 0x46 # CHECK: maddf.s $f2, $f3, $f4
 0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4
 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x10 0x08 0x22 0x46 # CHECK: sel.d $f0, $f1, $f2
 0x10 0x08 0x02 0x46 # CHECK: sel.s $f0, $f1, $f2
 0x35 0x10 0x64 0x00 # CHECK: seleqz $2, $3, $4
 0x37 0x10 0x64 0x00 # CHECK: selnez $2, $3, $4
 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
 0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

 0x41 0x60 0x60 0x00 # CHECK: di
 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x00 0x64 0x10 0xc5 # CHECK: lsa $2, $3, $4, 3
 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
 0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4

test/MC/Disassembler/Mips/mips64.txt

 # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s
 # CHECK: daddiu $11, $26, 31949
 0x67 0x4b 0x7c 0xcd
 
 # CHECK: daddiu $sp, $sp, -32
 0x67 0xbd 0xff 0xe0
 
 # CHECK: daddu $26, $1, $11
 0x00 0x2b 0xd0 0x2d
 
 # CHECK: ddiv $zero, $26, $22
 0x03 0x56 0x00 0x1e
 
 # CHECK: ddivu $zero, $9, $24
 0x01 0x38 0x00 0x1f
 
+# CHECK: dmfc0 $24, $10, 0
+0x40 0x38 0x50 0x00
+
 # CHECK: dmfc1 $2, $f14
 0x44 0x22 0x70 0x00
 
+# CHECK: dmtc0 $4, $10, 0
+0x40 0xa4 0x50 0x00
+
 # CHECK: dmtc1 $23, $f5
 0x44 0xb7 0x28 0x00
 
 # CHECK: dmult $11, $26
 0x01 0x7a 0x00 0x1c
 
 # CHECK: dmultu $23, $13
 0x02 0xed 0x00 0x1d

 0x00 0x1c 0x56 0x3a
 
 # CHECK: dsrlv $gp, $10, $23
 0x02 0xea 0xe0 0x16
 
 # CHECK: dsubu $gp, $27, $24
 0x03 0x78 0xe0 0x2f
 
+# CHECK: mfc0 $8, $15, 1
+0x40 0x08 0x80 0x04
+
+# CHECK: mtc0 $9, $15, 1
+0x40 0x89 0x78 0x01
+
 # CHECK: lw $27, -15155($1)
 0x8c 0x3b 0xc4 0xcd
 
 # CHECK: lui $1, 1
 0x3c 0x01 0x00 0x01
 
 # CHECK: lwu $3, -1746($3)
 0x9c 0x63 0xf9 0x2e

test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt

 0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
 0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
 0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
 0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
 0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
 0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
 0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18

 0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
 0x00 0x03 0xd1 0x4f # CHECK: lwxc1 $f12, $17($fp)
 0x18 0x00 0xa4 0x8c # CHECK: lw $4, 24($5)
 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5
 0x19 0x00 0x65 0x00 # CHECK: multu $3, $5

test/MC/Disassembler/Mips/mips64/valid-mips64.txt

 0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
 0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
 0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
 0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12

 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
 0x4f 0xd1 0x03 0x00 # CHECK: lwxc1 $f12, $17($fp)
 0x8c 0xa4 0x00 0x18 # CHECK: lw $4, 24($5)
 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5
 0x00 0x65 0x00 0x19 # CHECK: multu $3, $5

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt

 0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
 0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
 0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
 0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
 0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
 0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
 0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18

 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
 0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt

 0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
 0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
 0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
 0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12

 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt

 0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
 0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
 0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
 0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
 0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
 0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
 0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18

 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
 0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt

 0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
 0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
 0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
 0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12

 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt

 0x16 0xee 0xda 0x66 # CHECK: daddiu $26, $22, -4586
 0x2d 0x98 0x3f 0x00 # CHECK: daddu $19, $1, $ra
 0x9f 0x46 0x58 0x64 # CHECK: daddiu $24, $2, 18079
 0x3f 0x69 0x73 0x66 # CHECK: daddiu $19, $19, 26943
 0x25 0x90 0xd2 0x70 # CHECK: dclo $18, $6
 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
 0x1e 0x00 0x53 0x03 # CHECK: ddiv $zero, $26, $19
 0x1f 0x00 0x11 0x02 # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
 0x1c 0x00 0xe9 0x02 # CHECK: dmult $23, $9
 0x1d 0x00 0xa6 0x00 # CHECK: dmultu $5, $6
 0xb8 0x04 0x00 0x00 # CHECK: dsll $zero, $zero, 18
 0xb8 0x04 0x14 0x00 # CHECK: dsll $zero, $20, 18
 0x14 0x00 0x94 0x01 # CHECK: dsllv $zero, $20, $12
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18
 0xbc 0x04 0x00 0x00 # CHECK: dsll32 $zero, $zero, 18

 0xc6 0x23 0xe9 0xc4 # CHECK: lwc1 $f9, 9158($7)
 0x03 0x00 0x82 0x88 # CHECK: lwl $2, 3($4)
 0x10 0x00 0xa3 0x98 # CHECK: lwr $3, 16($5)
 0x00 0x05 0xcc 0x4d # CHECK: lwxc1 $f20, $12($14)
 0xea 0xa1 0x73 0x9c # CHECK: lwu $19, -24086($3)
 0x00 0x00 0xc7 0x70 # CHECK: madd $6, $7
 0x60 0x98 0xf9 0x4f # CHECK: madd.s $f1, $f31, $f19, $f25
 0x01 0x00 0xc7 0x70 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
 0x28 0x53 0x70 0x4e # CHECK: msub.s $f12, $f19, $f10, $f16
 0x05 0x00 0xc7 0x70 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x38 0x86 0x44 # CHECK: mtc1 $6, $f7
 0x11 0x00 0xe0 0x00 # CHECK: mthi $7
 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
 0x13 0x00 0xe0 0x00 # CHECK: mtlo $7
 0x02 0x62 0x2e 0x46 # CHECK: mul.d $f8, $f12, $f14
 0x42 0x32 0x07 0x46 # CHECK: mul.s $f9, $f6, $f7
 0x02 0x48 0xc7 0x70 # CHECK: mul $9, $6, $7
 0x18 0x00 0x65 0x00 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt

 0x66 0xda 0xee 0x16 # CHECK: daddiu $26, $22, -4586
 0x00 0x3f 0x98 0x2d # CHECK: daddu $19, $1, $ra
 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
 0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
 0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12

 0xc4 0xe9 0x23 0xc6 # CHECK: lwc1 $f9, 9158($7)
 0x88 0x82 0x00 0x03 # CHECK: lwl $2, 3($4)
 0x98 0xa3 0x00 0x10 # CHECK: lwr $3, 16($5)
 0x4d 0xcc 0x05 0x00 # CHECK: lwxc1 $f20, $12($14)
 0x9c 0x73 0xa1 0xea # CHECK: lwu $19, -24086($3)
 0x70 0xc7 0x00 0x00 # CHECK: madd $6, $7
 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
 0x70 0xc7 0x00 0x01 # CHECK: maddu $6, $7
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x44 0x06 0x38 0x00 # CHECK: mfc1 $6, $f7
 0x00 0x00 0x28 0x10 # CHECK: mfhi $5
 0x44 0x7e 0xc0 0x00 # CHECK: mfhc1 $fp, $f24
 0x00 0x00 0x28 0x12 # CHECK: mflo $5
 0x46 0x20 0x41 0x86 # CHECK: mov.d $f6, $f8
 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
 0x70 0xc7 0x00 0x04 # CHECK: msub $6, $7
 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
 0x70 0xc7 0x00 0x05 # CHECK: msubu $6, $7
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x44 0x86 0x38 0x00 # CHECK: mtc1 $6, $f7
 0x00 0xe0 0x00 0x11 # CHECK: mthi $7
 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
 0x00 0xe0 0x00 0x13 # CHECK: mtlo $7
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7
 0x70 0xc7 0x48 0x02 # CHECK: mul $9, $6, $7
 0x00 0x65 0x00 0x18 # CHECK: mult $3, $5

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

 0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25
 0x9e 0x10 0x64 0x00 # CHECK: ddiv $2, $3, $4
 0x9f 0x10 0x64 0x00 # CHECK: ddivu $2, $3, $4
 0x00 0x60 0x60 0x41 # CHECK: di
 0x00 0x60 0x7e 0x41 # CHECK: di $fp
 0x9a 0x10 0x64 0x00 # CHECK: div $2, $3, $4
 0x9b 0x10 0x64 0x00 # CHECK: divu $2, $3, $4
 0xd5 0x10 0x64 0x00 # CHECK: dlsa $2, $3, $4, 3
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0xde 0x10 0x64 0x00 # CHECK: dmod $2, $3, $4
 0xdf 0x10 0x64 0x00 # CHECK: dmodu $2, $3, $4
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0xdc 0x10 0x64 0x00 # CHECK: dmuh $2, $3, $4
 0xdd 0x10 0x64 0x00 # CHECK: dmuhu $2, $3, $4
 0x9c 0x10 0x64 0x00 # CHECK: dmul $2, $3, $4
 0x9d 0x10 0x64 0x00 # CHECK: dmulu $2, $3, $4
 0x20 0x60 0x60 0x41 # CHECK: ei
 0x20 0x60 0x6e 0x41 # CHECK: ei $14
 0x09 0xfc 0x80 0x00 # CHECK: jalr.hb $4
 0x09 0x24 0xa0 0x00 # CHECK: jalr.hb $4, $5

 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
 0x98 0x18 0x24 0x46 # CHECK: maddf.d $f2, $f3, $f4
 0x98 0x18 0x04 0x46 # CHECK: maddf.s $f2, $f3, $f4
 0x1d 0x10 0x24 0x46 # CHECK: max.d $f0, $f2, $f4
 0x1d 0x10 0x04 0x46 # CHECK: max.s $f0, $f2, $f4
 0x1f 0x10 0x24 0x46 # CHECK: maxa.d $f0, $f2, $f4
 0x1f 0x10 0x04 0x46 # CHECK: maxa.s $f0, $f2, $f4
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x1c 0x10 0x24 0x46 # CHECK: min.d $f0, $f2, $f4
 0x1c 0x10 0x04 0x46 # CHECK: min.s $f0, $f2, $f4
 0x1e 0x10 0x24 0x46 # CHECK: mina.d $f0, $f2, $f4
 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
 0xd8 0x10 0x64 0x00 # CHECK: muh $2, $3, $4
 0xd9 0x10 0x64 0x00 # CHECK: muhu $2, $3, $4
 0x98 0x10 0x64 0x00 # CHECK: mul $2, $3, $4
 0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
 0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
 0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4
 0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x7e 0x60 0x00 # CHECK: di $fp
 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4
 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
 0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3
+0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4
 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
+0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
 0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4
 0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4
 0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4
 0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
 0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14

 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4
 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4
 0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4
 0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4
 0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4
 0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4
+0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4
 0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4
 0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4
 0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4
 0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4
 0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4
 0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4
 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4
+0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4
 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4
 0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4
 0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4
 0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4

test/MC/Mips/mips-cop0-reginfo.s

+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -filetype=obj %s -o - | \
+# RUN:   llvm-readobj -sections -section-data - | \
+# RUN:     FileCheck %s -check-prefix=CHECK
+  mfc0  $16, $15, 1
+  mfc0  $16, $16, 1
+
+
+# Checking for the coprocessor 0's register usage was recorded
+# and emitted.
+# CHECK:  Section {
+# CHECK:     Index: 5
+# CHECK:     Name: .reginfo (27)
+# CHECK:     Type: SHT_MIPS_REGINFO (0x70000006)
+# CHECK:     Flags [ (0x2)
+# CHECK:       SHF_ALLOC (0x2)
+# CHECK:     ]
+# CHECK:     Address: 0x0
+# CHECK:     Offset: 0x50
+# CHECK:     Size: 24
+# CHECK:     Link: 0
+# CHECK:     Info: 0
+# CHECK:     AddressAlignment: 4
+# CHECK:     EntrySize: 24
+# CHECK:     SectionData (
+# CHECK:       0000: 00010000 00018000 00000000 00000000  |................|
+# CHECK:       0010: 00000000 00000000                    |........|
+# CHECK:     )
+# CHECK:   }

test/MC/Mips/mips32/valid.s

a:
         lwc1      $f16,10225($k0)
         lwc2      $18,-841($a2)        # CHECK: lwc2 $18, -841($6)     # encoding: [0xc8,0xd2,0xfc,0xb7]
         lwl       $s4,-4231($15)
         lwr       $zero,-19147($gp)
         madd      $s6,$13
         madd      $zero,$9
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $s8,$a0
         move      $25,$a2
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
         movn      $v1,$s1,$s0
         movn.d    $f27,$f21,$k0
         movn.s    $f12,$f0,$s7
         movt      $zero,$s4,$fcc5
         movt.d    $f0,$f2,$fcc0
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2
         mult      $sp,$s4

test/MC/Mips/mips32r2/valid.s

a:
         lwr       $zero,-19147($gp)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         madd.d    $f18,$f19,$f26,$f20
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $s8,$a0
a:
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msub.d    $f10,$f1,$f31,$f18
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1     # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2

test/MC/Mips/mips32r3/valid.s

a:
         lwr       $zero,-19147($gp)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         madd.d    $f18,$f19,$f26,$f20
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $s8,$a0
a:
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msub.d    $f10,$f1,$f31,$f18
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2

test/MC/Mips/mips32r5/valid.s

a:
         lwr       $zero,-19147($gp)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         madd.d    $f18,$f19,$f26,$f20
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $s8,$a0
a:
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msub.d    $f10,$f1,$f31,$f18
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2

test/MC/Mips/mips32r6/valid.s

a:
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
         lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]
         lwpc    $2,268           # CHECK: lwpc $2, 268     # encoding: [0xec,0x48,0x00,0x43]
         lwupc   $2,268           # CHECK: lwupc $2, 268    # encoding: [0xec,0x50,0x00,0x43]
+        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1  # encoding: [0x40,0x89,0x78,0x01]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
         maddf.s $f2,$f3,$f4      # CHECK: maddf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x98]
         maddf.d $f2,$f3,$f4      # CHECK: maddf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x98]
         msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
         msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]

test/MC/Mips/mips64/valid.s

a:
         dclz      $s0,$25              # CHECK: dclz $16, $25  # encoding: [0x73,0x30,0x80,0x24]
         deret
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10, $16, 2          # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4, $10, 0           # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
         dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
         dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
         dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
a:
         lwu       $s3,-24086($v1)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         maddu     $s3,$gp
         maddu     $24,$s2
         madd.d    $f18, $f22, $f26, $f20  # encoding: [0x4e,0xd4,0xd4,0xa1]
         madd.s    $f2, $f30, $f18, $f24   # encoding: [0x4f,0xd8,0x90,0xa0]
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $a0,$a3
         move      $s5,$a0
a:
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msubu     $15,$a1
         msub.d    $f10, $f2, $f30, $f18   # encoding: [0x4c,0x52,0xf2,0xa9]
         msub.s    $f12, $f18, $f10, $f16  # encoding: [0x4e,0x50,0x53,0x28]
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1                # CHECK: mtc0 $9, $15, 1     # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2
         mult      $sp,$s4

test/MC/Mips/mips64r2/valid.s

a:
         di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
         di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10,$16,2            # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4,$10,0             # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
         dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
         dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
         dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
a:
         lwr       $zero,-19147($gp)
         lwu       $s3,-24086($v1)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $a0,$a3
a:
         movt.d    $f0,$f2,$fcc0
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1     # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2

test/MC/Mips/mips64r3/valid.s

a:
         di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
         di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10, $16, 2          # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4, $10, 0           # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
         dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
         dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
         dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
a:
         lwr       $zero,-19147($gp)
         lwu       $s3,-24086($v1)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $a0,$a3
a:
         movt.d    $f0,$f2,$fcc0
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2

test/MC/Mips/mips64r5/valid.s

a:
         di        $s8                  # CHECK: di  $fp        # encoding: [0x41,0x7e,0x60,0x00]
         di                             # CHECK: di             # encoding: [0x41,0x60,0x60,0x00]
         ddiv      $zero,$k0,$s3
         ddivu     $zero,$s0,$s1
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
+        dmfc0     $10, $16, 2          # CHECK: dmfc0 $10, $16, 2           # encoding: [0x40,0x2a,0x80,0x02]
         dmfc1     $12,$f13
+        dmtc0     $4, $10, 0           # CHECK: dmtc0 $4, $10, 0            # encoding: [0x40,0xa4,0x50,0x00]
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
         dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
         dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
         dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
a:
         lwr       $zero,-19147($gp)
         lwu       $s3,-24086($v1)
         lwxc1     $f12,$s1($s8)
         madd      $s6,$13
         madd      $zero,$9
         madd.s    $f1,$f31,$f19,$f25
         maddu     $s3,$gp
         maddu     $24,$s2
-        mfc0      $a2,$14,1
+        mfc0      $8,$15,1             # CHECK: mfc0 $8, $15, 1        # encoding: [0x40,0x08,0x78,0x01]
         mfc1      $a3,$f27
         mfhc1     $s8,$f24
         mfhi      $s3
         mfhi      $sp
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
         move      $a0,$a3
a:
         movt.d    $f0,$f2,$fcc0
         movt.s    $f30,$f2,$fcc1
         movz      $a1,$s6,$9
         movz.d    $f12,$f29,$9
         movz.s    $f25,$f7,$v1
         msub      $s7,$k1
         msub.s    $f12,$f19,$f10,$f16
         msubu     $15,$a1
-        mtc0      $9,$29,3
+        mtc0      $9,$15,1             # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         mtc1      $s8,$f9
         mthc1     $zero,$f16
         mthi      $s1
         mtlo      $sp
         mtlo      $25
         mul       $s0,$s4,$at
         mul.d     $f20,$f20,$f16
         mul.s     $f30,$f10,$f2

test/MC/Mips/mips64r6/valid.s

a:
         dclz    $s0,$25          # CHECK: dclz $16, $25          # encoding: [0x03,0x20,0x80,0x52]
         ddiv    $2,$3,$4         # CHECK: ddiv $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9e]
         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
         di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5]
+        dmfc0   $10, $16, 2      # CHECK: dmfc0 $10, $16, 2  # encoding: [0x40,0x2a,0x80,0x02]
         dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
         dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
+        dmtc0   $4, $10, 0       # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00]
         dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdc]
         dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
         dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9c]
         dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
         dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
         dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
         dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsubu   $14,-4586        # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
a:
         max.d   $f0, $f2, $f4    # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
         max.s   $f0, $f2, $f4    # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
         maxa.d  $f0, $f2, $f4    # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
         maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
         min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
         min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
         mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
         mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+        mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
         msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         or      $2, 4            # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
         pref    1, 8($5)         # CHECK: pref 1, 8($5)          # encoding: [0x7c,0xa1,0x04,0x35]