Change Details

We have a trunc/(shl, srl, sra) combine in the DAG. The SHL is already handled by a generic combine, but there was no combine for right-shifts.

This combine only handled left shifts, but now it can handle right shifts as well. It handles right shifts conservatively and only truncates them to the size returned by TLI. AMDGPU benefits from always lowering shifts to 32 bits for instance, but AArch64 would rather keep them at 64 bits.

We have a trunc/(shlThis combine only handled left shifts, srl,but now it can handle right shifts as well. sra) combine in the DAG. The SHL is already handled by a generic combinIt handles right shifts conservatively and only truncates them to the size returned by TLI. AMDGPU benefits from always lowering shifts to 32 bits for instance, but there was no combine for right-shiftsAArch64 would rather keep them at 64 bits.