The implementation follows the MIPS backend and expands the
pseudo instruction directly during asm parsing. As the result, only
real MC instructions are emitted to the MCStreamer. Additionally,
PseudoLI instructions are emitted during codegen. The actual
expansion to real instructions is performed during MI to MC lowering.
Currently only support for 32-bit constants is implemented.
Support for 64-bit constants (on RV64) will be added when the overall
approach is approved. Comments are welcome. :)
Note also that the emitLoadImm functions need a location where they
can be shared between the RISCVAsmParser and the RISCVAsmPrinter.
The only RISCV libraries they currently share are RISCVDesc and