Currently the custom SGPR spill lowering pass would
spill SGPRs into physical VGPR lanes and the remaining
VGPRs are used by regalloc for vector regclass allocation.
This currently imposes many restrictions that we end up
with unsuccessful SGPR spilling when there won't be
enough VGPRs and we are forced to spill the remaining
spills into memory during PEI. The custom spilling during
PEI has many edge cases and often breaks the compiler time
This patch implements spilling SGPRs into virtual VGPR
lanes. Since we now split the register allocation for
SGPRs and VGPRs, the virtual registers introduced for
spill lanes would get allocated automatically in the
following regalloc invocation.
Spill to virtual registers will always be successful,
even at high-pressure situations and thereby avoiding
most of the edge cases in the PEI apart from the
difficulty with custom SGPR spills for special register.