HomePhabricator

[InstCombine] Fix miscompile bug in canEvaluateShuffled

Description

[InstCombine] Fix miscompile bug in canEvaluateShuffled

Summary:
Add restrictions in canEvaluateShuffled to prevent that we for example
transform

%0 = insertelement <2 x i16> undef, i16 %a, i32 0
%1 = srem <2 x i16> %0, <i16 2, i16 1>
%2 = shufflevector <2 x i16> %1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>

into

%1 = insertelement <2 x i16> undef, i16 %a, i32 1
%2 = srem <2 x i16> %1, <i16 undef, i16 2>

as having an undef denominator makes the srem undefined (for all
vector elements).

Fixes: https://bugs.llvm.org/show_bug.cgi?id=43689

Reviewers: spatel, lebedev.ri

Reviewed By: spatel, lebedev.ri

Subscribers: lebedev.ri, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69038

Details

Committed
bjopeFri, Oct 18, 12:42 AM
Reviewer
spatel
Differential Revision
D69038: [InstCombine] Fix miscompile bug in canEvaluateShuffled
Parents
rL375207: [InstCombine] Pre-commit of test case showing miscompile bug in…
Branches
Unknown
Tags
Unknown