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[MachinePipeliner] Fix order for nodes with Anti dependence in same cycle

Description

[MachinePipeliner] Fix order for nodes with Anti dependence in same cycle

Summary:
Problem exposed in PowerPC functional testing.

We did not consider Anti dependence for nodes in same cycle,
so we may end up generating bad machine code.
eg: the reduced test won't verify.

    • Bad machine code: Using an undefined physical register ***
  • function: lame_encode_buffer_interleaved
  • basic block: %bb.4 (0x4bde4e12928)
  • instruction: %29:gprc = ADDZE %27:gprc, implicit-def dead $carry, implicit $carry
  • operand 3: implicit $carry

Reviewers: bcahoon, kparzysz, hfinkel

Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64192

Details

Committed
jsjiJul 11 2019, 6:59 PM
Differential Revision
D64192: [MachinePipeliner] Fix order for nodes with Anti dependence in same cycle
Parents
rL365858: Handle IntToPtr in isBytewiseValue
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