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[ARM] DLS/LE low-overhead loop code generation

Description

[ARM] DLS/LE low-overhead loop code generation

Introduce three pseudo instructions to be used during DAG ISel to
represent v8.1-m low-overhead loops. One maps to set_loop_iterations
while loop_decrement_reg is lowered to two, so that we can separate
the decrement and branching operations. The pseudo instructions are
expanded pre-emission, where we can still decide whether we actually
want to generate a low-overhead loop, in a new pass:
ARMLowOverheadLoops. The pass currently bails, reverting to an sub,
icmp and br, in the cases where a call or stack spill/restore happens
between the decrement and branching instructions, or if the loop is
too large.

Differential Revision: https://reviews.llvm.org/D63476

Details

Committed
sam_parkerJun 25 2019, 3:45 AM
Differential Revision
D63476: [ARM] DLS/LE low-overhead loop code generation
Parents
rL364287: [docs][llvm-cxxfilt] Write llvm-cxxfilt documentation
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Event Timeline

Thanks for letting me know. This must be because I reordered the pass and didn't update the mir tests - I'll get onto it now.

This should now be fixed in rL364323.

This should now be fixed in rL364323.

Thanks @samparker !