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[AArch64][SVE2] Asm: add various bitwise shift instructions

Description

[AArch64][SVE2] Asm: add various bitwise shift instructions

Summary:
This patch adds support for the SVE2 saturating/rounding bitwise shift
left (predicated) group of instructions:

  • SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL, SQSHLR, UQSHLR, SQRSHLR, UQRSHLR

Immediate forms of the SQSHL and UQSHL instructions are also added to
the existing SVE bitwise shift by immediate (predicated) group, as well
as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in
this group are encoded similarly and are implemented using the same
TableGen class with a minimal change (1 bit in encoding).

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62140

Details

Committed
c-rhodesMay 24 2019, 2:17 AM
Reviewer
SjoerdMeijer
Differential Revision
D62140: [AArch64][SVE2] Asm: add various bitwise shift instructions
Parents
rL361611: [AArch64][SVE2] Asm: add saturating add/sub instructions
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