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Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector shuffle…

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Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1."

The code to materialize a mask from a constant pool load tried to use a 128 bit
LDR to load a 64 bit constant pool entry, which was 8 byte aligned. This resulted
in a link failure in the NEON tests in the test suite since the LDR address was
unaligned. This change fixes that to instead emit a 64 bit LDR if the entry is
64 bit, before converting back to a 128 bit register for the TBL.

Details

Committed
aemersonMar 4 2019, 11:16 AM
Parents
rL355325: [MC] Teach ELFObjectWriter that parse-time variables do not appear in
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