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DAG: Handle odd vector sizes in calling conv splitting

Description

DAG: Handle odd vector sizes in calling conv splitting

This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.

Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.

This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.

Details

Committed
arsenmSep 10 2018, 4:49 AM
Parents
rL341800: [clangd] Add symbol slab size to index memory consumption estimates
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