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[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel…

Description

[X86] Correct the scheduling data for register forms of XCHG and XADD on Intel CPUs.

The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register.

XADD is probably 2 moves and an add also using a temporary register.

Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available.

Details

Committed
ctopperApr 19 2018, 11:00 AM
Parents
rL330348: [Reassociate] fix formatting; NFC
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