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[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits

Description

[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits

These immediates can be materialised with just an lui, rather than an lui+addi
pair.

Details

Committed
asbApr 18 2018, 1:34 PM
Parents
rL330292: [RuntimeDebugBuilder] Print vectors passed without withspaces
Branches
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