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AMDGPU: Do not combine loads/store across physreg defs

Description

AMDGPU: Do not combine loads/store across physreg defs

Summary:
Since this pass operates on machine SSA form, this should only really
affect M0 in practice.

Fixes various piglit variable-indexing/vs-varying-array-mat4-index-*

Change-Id: Ib2a1dc3a8d7b08225a8da49a86f533faa0986aa8
Fixes: r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4")

Reviewers: arsenm, mareko, rampitec

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D40343

Details

Committed
nhaFeb 21 2018, 5:31 AM
Differential Revision
D40343: AMDGPU: Do not combine loads/store across physreg defs
Parents
rL325676: [AMDGPU][MC] Added lds support for MUBUF instructions
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