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AMDGPU: Add 32-bit constant address space

Description

AMDGPU: Add 32-bit constant address space

Note: This is a candidate for LLVM 6.0, because it was planned to be

in that release but was delayed due to a long review period.

Merge conflict in release_60 - resolution:

Add "-p6:32:32" into the second (non-amdgiz) string.

Only scalar loads support 32-bit pointers. An address in a VGPR will
fail to compile. That's OK because the results of loads will only be used
in places where VGPRs are forbidden.

Updated AMDGPUAliasAnalysis and used SReg_64_XEXEC.
The tests cover all uses cases we need for Mesa.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D41651

Details

Committed
marekoFeb 7 2018, 8:01 AM
Differential Revision
D41651: AMDGPU: Add 32-bit constant address space
Parents
rL324486: AMDGPU: Remove the s_buffer workaround for GFX9 chips
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