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[AArch64] Avoid unnecessary vector byte-swapping in big-endian

Description

[AArch64] Avoid unnecessary vector byte-swapping in big-endian

Summary:
Loads/stores of some NEON vector types are promoted to other vector
types with different lane sizes but same vector size. This is not a
problem in little-endian but, when in big-endian, it requires
additional byte reversals required to preserve the lane ordering
while keeping the right endianness of the data inside each lane.
For example:

%1 = load <4 x half>, <4 x half>* %p

results in the following assembly:

ld1 { v0.2s }, [x1]
rev32 v0.4h, v0.4h

This patch changes the promotion of these loads/stores so that the
actual vector load/store (LD1/ST1) takes care of the endianness
correctly and there is no need for further byte reversals. The
previous code now results in the following assembly:

ld1 { v0.4h }, [x1]

Reviewers: olista01, SjoerdMeijer, efriedma

Reviewed By: efriedma

Subscribers: aemerson, rengolin, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D42235

Details

Committed
pabbar01Jan 24 2018, 6:13 AM
Reviewer
efriedma
Differential Revision
D42235: [AArch64] Avoid unnecessary vector byte-swapping in big-endian
Parents
rL323324: [Hexagon] Remove unused HexagonISD opcodes, NFC
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