HomePhabricator

[AArch64] Change order of candidate FMLS patterns

Description

[AArch64] Change order of candidate FMLS patterns

r319980 added new patterns to the machine combiner for transforming (fsub (fmul
x y) z) into (fmla (fneg z) x y). That is, fsub's where the first source
operand is an fmul are transformed. We previously only matched the case where
the second source operand of an fsub was an fmul, transforming (fsub z (fmul x
y)) into (fmls z x y). Now, if we have an fsub where both source operands are
fmuls, both of the above patterns are applicable.

However, the order in which we add the patterns to the list of candidates
determines the transformation that takes place, since only the first pattern
that matches will be used. This patch changes the order these two patterns are
added to the list of candidates such that we prefer the case where the second
source operand is an fmul (the fmls case), rather than the other one (the
fmla/fneg case). When both source operands are fmuls, this ordering results in
fewer instructions.

Differential Revision: https://reviews.llvm.org/D41587

Details

Committed
mssimpsoDec 27 2017, 7:25 AM
Differential Revision
D41587: [AArch64] Change order of candidate FMLS patterns
Parents
rL321490: [X86] Fix vmul combine for AVX1 targets.
Branches
Unknown
Tags
Unknown