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[RISCV] Use register X0 (ZERO) for constant 0

Description

[RISCV] Use register X0 (ZERO) for constant 0

The obvious approach of defining a pattern like the one below actually doesn't
work:
def : Pat<(i32 0), (i32 X0)>;

As was noted when Lanai made this change (https://reviews.llvm.org/rL288215),
attempting to handle the constant 0 in tablegen leads to assertions due to a
physical register being used where a virtual register is expected.

Details

Committed
asbNov 21 2017, 12:23 AM
Parents
rL318737: [RISCV] Support and tests for a variety of additional LLVM IR constructs
Branches
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Event Timeline

glasnak added inline comments.
/llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
77

This feels strange. ReplaceNode returns void and you're also returning void, is this intended?

asb added inline comments.Nov 21 2017, 4:03 AM
/llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
77

It's correct in that I do want an early return and am expecting to return void, but you're right it's a confusing way to do it. I've cleaned up this code in rL318757. Thanks!