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X86 ISel: Basic support for variable-index vector permutations

Description

X86 ISel: Basic support for variable-index vector permutations

Summary:
Try to lower a BUILD_VECTOR composed of extract-extract chains that can be
reasoned to be a permutation of a vector by indices in a non-constant vector.

We saw this pattern created by ISPC, which resolts to creating it due to the
requirement that shufflevector's mask operand be a *constant* vector.
I didn't check this but we could possibly use this pattern for lowering the X86 permute
C-instrinsics instead of llvm.x86 instrinsics.

This change can be followed by more improvements:

  1. Handle vectors with undef elements.
  2. Utilize pshufb and zero-mask-blending to support more effiecient construction of vectors with constant-0 elements.
  3. Use smaller-element vectors of same width, and "interpolate" the indices, when no native operation available.

Reviewers: RKSimon, craig.topper

Reviewed By: RKSimon

Subscribers: chandlerc, DavidKreitzer

Differential Revision: https://reviews.llvm.org/D39126

Details

Committed
zviNov 6 2017, 12:25 AM
Reviewer
RKSimon
Differential Revision
D39126: X86 ISel: Basic support for variable-index vector permutations
Parents
rL317462: Revert "adding a pattern for broadcastm"
Branches
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Tags
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Event Timeline

@zvi @craig.topper I think the PSHUFB operands are swapped - do you agree? (VPERMV is a weird one....) If so we need to get this fixed in 6.000

/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
7818

It looks like this in correct - I think it should be:

if (VT == MVT::v16i8)
  return DAG.getNode(X86ISD::PSHUFB, SDLoc(V), VT, SrcVec, IndicesVec);
return DAG.getNode(X86ISD::VPERMV, SDLoc(V), VT, IndicesVec, SrcVec);