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[RISCV] Add support for all RV32I instructions

Description

[RISCV] Add support for all RV32I instructions

This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).

Differential Revision: https://reviews.llvm.org/D23566

Details

Committed
asbSep 17 2017, 7:27 AM
Differential Revision
D23566: [RISCV 8/10] Add support for all RV32I instructions
Parents
rL313484: [GlobalISel][X86] refactoring X86InstructionSelector.cpp .NFC.
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