[AArch64][Falkor] Fix some sched details.

Description

[AArch64][Falkor] Fix some sched details.

  • Remove all uses of base sched model entries and set them all to Unsupported so all the opcodes are described in AArch64SchedFalkorDetails.td.
  • Remove entries for unsupported half-float opcodes.
  • Remove entries for unsupported LSE extension opcodes.
  • Add entry for MOVbaseTLS (and set Sched in base td file entry to WriteSys) and a few other pseudo ops.
  • Fix a few FP load/store with reg offset entries to use the LSLfast predicates.
  • Add Q size BIF/BIT/BSL entries.
  • Fix swapped Q/D sized CLS/CLZ/CNT/RBIT entires.
  • Fix pre/post increment address register latency (this operand is always dest 0).
  • Fix swapped FCVTHD/FCVTHS/FCVTDH/FCVTDS entries.
  • Fix XYZ resource over usage on LD[1-4] opcodes.

Details

Committed
gberryMay 28 2017, 2:48 PM
Parents
rL304107: [coroutines] Support "coroutines" feature in module map requires clause
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