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This patch closes PR#32216: Better testing of schedule model instruction…
Audit RequiredrL300311

Description

This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs.
The details are here: https://reviews.llvm.org/D30941

Details

Auditors
grosbach
Bigcheese
Committed
avt77Apr 14 2017, 12:44 AM
Parents
rL300310: [LV] Remove implicit single basic block assumption
Branches
Unknown
Tags
Unknown

Event Timeline

atrick added a subscriber: atrick.Apr 21 2017, 2:40 PM
atrick added inline comments.
/llvm/trunk/lib/CodeGen/TargetSchedule.cpp
370

Why is this returning instead of continuing?

avt77 added inline comments.Apr 22 2017, 12:42 AM
/llvm/trunk/lib/CodeGen/TargetSchedule.cpp
370

I thought it means we have wrong model but maybe you're right and we should simply continue. Other opinios about the issue?

atrick added inline comments.Apr 22 2017, 12:59 AM
/llvm/trunk/lib/CodeGen/TargetSchedule.cpp
370

In the target description, by default ResourceCycles=1. However, ResourceCycles=0 could be used to mean that the resource must be available in order to issue the instruction, but won't actually consume that resource. Strange, but possibly useful.