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[mips][msa] Implement f16 support

Description

[mips][msa] Implement f16 support

The MIPS MSA ASE provides instructions to convert to and from half precision
floating point. This patch teaches the MIPS backend to treat f16 as a legal
type and how to promote such values to f32 for the usual set of operations.

As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during
type legalization.

Reviewers: zoran.jovanvoic, vkalintiris

Differential Revision: https://reviews.llvm.org/D26398

Details

Committed
sdardisNov 18 2016, 8:17 AM
Differential Revision
D26398: [mips][msa] Implement f16 support
Parents
rL287348: [X86][AVX512] Split AVX512F/AVX512VL tests to demonstrate missed int2fp…
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