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[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td

Description

[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td

For now, only add instruction definitions for basic ALU operations. Our
initial target is a working MC layer rather than codegen, so appropriate
SelectionDAG patterns will come later.

Differential Revision: https://reviews.llvm.org/D23561

Details

Committed
asbNov 1 2016, 4:40 PM
Differential Revision
D23561: [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td
Parents
rL285768: AMDGPU: Handle CopyToReg in getOperandRegClass
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