AArch64: TableGenerate system instruction operands.

Description

AArch64: TableGenerate system instruction operands.

The way the named arguments for various system instructions are handled at the
moment has a few problems:

  • Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  • That weird Mapping class that I have no idea what I was on when I thought it was a good idea.
  • Searches are performed linearly through the entire list.
  • We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example).
  • The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

Details

Committed
tnorthoverJul 5 2016, 2:23 PM
Parents
rL274575: TableGen: promote "code" type from syntactic sugar.
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