Assume lane masks are always precise

Description

Assume lane masks are always precise

Allowing imprecise lane masks in case of more than 32 sub register lanes
lead to some tricky corner cases, and I need another bugfix for another
one. Instead I rather declare lane masks as precise and let tablegen
abort if we do not have enough bits.

This does not affect any in-tree target, even AMDGPU only needs 16 lanes
at the moment. If the 32 lanes turn out to be a problem in the future,
then we can easily change the LaneBitmask typedef to uint64_t.

Differential Revision: http://reviews.llvm.org/D14557

Details

Committed
matzeNov 16 2015, 4:50 PM
Differential Revision
D14557: Assume lane masks are precise
Parents
rL253278: Fix indentation
Branches
Unknown
Tags
Unknown