ARM: teach AAPCS-VFP to deal with Cortex-M4.

Description

ARM: teach AAPCS-VFP to deal with Cortex-M4.

Cortex-M4 only has single-precision floating point support, so any LLVM
"double" type will have been split into 2 i32s by now. Fortunately, the
consecutive-register framework turns out to be precisely what's needed to
reconstruct the double and follow AAPCS-VFP correctly!

rdar://problem/17012966

Details

Committed
tnorthoverMay 27 2014, 3:43 AM
Parents
rL209649: Adds child traversal matchers for IfStmt's then and else branches.
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