[mips][mips64r6] Add b[on]vc
AuditedrL209415

Description

[mips][mips64r6] Add b[on]vc

Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.

  • da[ht]i only take two operands according to the spec, not three.
  • DecodeBranchTarget2[16] correctly handles wider immediates than simm16
    • Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them.
  • Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary.

DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.

jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.

Depends on D3760

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3761

Details

Auditors
dsanders
Committed
dsandersMay 22 2014, 4:23 AM
Reviewer
vmedic
Differential Revision
D3761: [mips][mips64r6] Add b[on]vc
Parents
rL209414: [ASan/Win] Add a comment about DCL-using-static vs threads
Branches
Unknown
Tags
Unknown
dsanders accepted this commit.Jul 21 2014, 9:28 AM