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[AArch64][SVE] Fold vector ZExt/SExt into gather loads where possible

Authored by joechrisellis on Mar 4 2021, 1:06 AM.

Description

[AArch64][SVE] Fold vector ZExt/SExt into gather loads where possible

This commit folds sxtw'd or uxtw'd offsets into gather loads where
possible with a DAGCombine optimization.

As an example, the following code:

1	#include <arm_sve.h>
2
3	svuint64_t func(svbool_t pred, const int32_t *base, svint64_t offsets) {
4	  return svld1sw_gather_s64offset_u64(
5	    pred, base, svextw_s64_x(pred, offsets)
6	  );
7	}

would previously lower to the following assembly:

sxtw	z0.d, p0/m, z0.d
ld1sw	{ z0.d }, p0/z, [x0, z0.d]
ret

but now lowers to:

ld1sw   { z0.d }, p0/z, [x0, z0.d, sxtw]
ret

Differential Revision: https://reviews.llvm.org/D97858

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