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[analyzer] Add system header simulator a symmetric random access iterator…

Authored by gamesh411 on Jul 6 2020, 7:25 AM.

Description

[analyzer] Add system header simulator a symmetric random access iterator operator+

Summary:
Random access iterators must handle operator+, where the iterator is on the
RHS. The system header simulator library is extended with these operators.

Reviewers: Szelethus

Subscribers: whisperity, xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, Charusso, steakhal, martong, ASDenysPetrov, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D83226