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[SYCL] Enable FPGA memory attributes

Authored by vmaksimo on Mar 19 2019, 11:56 AM.

Description

[SYCL] Enable FPGA memory attributes

This patch introduces the following FPGA memory attributes:

  • register
  • memory
  • numbanks
  • bankwidth

Signed-off-by: Vladimir Lazarev <vladimir.lazarev@intel.com>
Signed-off-by: Viktoria Maksimova <viktoria.maksimova@intel.com>

Details

Committed
Vladimir Lazarev <vladimir.lazarev@intel.com>Mar 22 2019, 12:11 PM
Parents
rG0738099b4ab8: [SYCL] Add multiple target binaries support.
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Event Timeline

Vladimir Lazarev <vladimir.lazarev@intel.com> committed rGfbffaab85dae: [SYCL] Enable FPGA memory attributes (authored by vmaksimo).Mar 22 2019, 12:11 PM