HomePhabricator

[InstCombine] sink sext after ashr

Authored by spatel on Aug 15 2017, 11:25 AM.

Description

[InstCombine] sink sext after ashr

Narrow ops are better for bit-tracking, and in the case of vectors,
may enable better codegen.

As the trunc test shows, this can allow follow-on simplifications.

There's a block of code in visitTrunc that deals with shifted ops
with FIXME comments. It may be possible to remove some of that now,
but I want to make sure there are no problems with this step first.

http://rise4fun.com/Alive/Y3a

Name: hoist_ashr_ahead_of_sext_1

%s = sext i8 %x to i32
%r = ashr i32 %s, 3  ; shift value is < than source bit width
=>
%a = ashr i8 %x, 3
%r = sext i8 %a to i32

Name: hoist_ashr_ahead_of_sext_2

%s = sext i8 %x to i32
%r = ashr i32 %s, 8  ; shift value is >= than source bit width
=>
%a = ashr i8 %x, 7   ; so clamp this shift value
%r = sext i8 %a to i32

Name: junc_the_trunc

%a = sext i16 %v to i32
%s = ashr i32 %a, 18
%t = trunc i32 %s to i16
=>
%t = ashr i16 %v, 15

llvm-svn: 310942

Details

Committed
spatelAug 15 2017, 11:25 AM
Parents
rGbb30377c5a8e: [Polly] [GPUJIT] Set min size to 1 on CUDA allocation calls. [NFC]
Branches
Unknown
Tags
Unknown