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[SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD…

Authored by RKSimon on Jan 13 2020, 4:01 AM.

Description

[SelectionDAG] ComputeKnownBits add getValidMinimumShiftAmountConstant() ISD::SHL support

As mentioned on D72573

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Committed
RKSimonJan 13 2020, 4:02 AM
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rG7efc7ca8edf6: [X86][SSE] Add knownbits test showing missing…
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nikic added a subscriber: nikic.Jan 13 2020, 6:46 AM
nikic added inline comments.
/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2839

This looks like it could potentially compute a worse result than below. Shouldn't both be combined? I.e. the maximum of Known.countMinTrailingZeros() and ShMinAmt?

RKSimon added inline comments.Jan 13 2020, 7:37 AM
/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2839

Do you have a test case?

nikic added inline comments.Jan 13 2020, 7:50 AM
/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2839

Don't have a build handy right now, but something along these lines might work.

define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0)  {
  %1 = and <4 x i32> %a0, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
  %2 = shl <4 x i32> %1, <i32 2, i32 3, i32 4, i32 5>
  %3 = add <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
  ret <4 x i32> %3
}

The and here should guarantee 16 low zero bits, while the min shift amount only guarantees 2.

RKSimon marked an inline comment as done.Jan 13 2020, 10:31 AM
RKSimon added inline comments.
/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
2839

Cheers - looking at this now