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[ELF][RISCV] Support RISC-V in getBitcodeMachineKind

Authored by kito-cheng on Jul 2 2019, 7:13 PM.

Description

[ELF][RISCV] Support RISC-V in getBitcodeMachineKind

Add Triple::riscv64 and Triple::riscv32 to getBitcodeMachineKind for get right
e_machine during LTO.

Reviewed By: ruiu, MaskRay

Differential Revision: https://reviews.llvm.org/D52165

llvm-svn: 364996

Details

Committed
kito-chengJul 2 2019, 7:13 PM
Reviewer
ruiu
Differential Revision
D52165: [RISCV] Support RISC-V in getBitcodeMachineKind
Parents
rG80177ca5a9b0: [AMDGPU] Enable serializing of argument info.
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