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[ARM] Support inline assembler constraints for MVE.

Authored by simon_tatham on Jun 25 2019, 9:49 AM.

Description

[ARM] Support inline assembler constraints for MVE.

"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.

Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.

Reviewers: dmgreen, samparker, SjoerdMeijer

Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D60709

llvm-svn: 364331

Details

Committed
simon_tathamJun 25 2019, 9:49 AM
Differential Revision
D60709: [ARM] Support inline assembler constraints for MVE.
Parents
rG88139c143c5f: [AVR] Adjust to Register class change
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