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[llvm][aarch64] SVE addressing modes.

Authored by fpetrogalli on Jan 28 2020, 12:37 PM.

Description

[llvm][aarch64] SVE addressing modes.

Summary:
Added register + immediate and register + register addressing modes for the following intrinsics:

  1. Masked load and stores:
    • Sign and zero extended load and truncated stores.
    • No extension or truncation.
  2. Masked non-temporal load and store.

Reviewers: andwar, efriedma

Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74254

Details

Committed
fpetrogalliFeb 21 2020, 12:02 PM
Differential Revision
D74254: [llvm][aarch64] SVE addressing modes.
Parents
rG69d757c0e8ff: Move StandardOps/Ops.h to StandardOps/IR/Ops.h
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