[AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2

Authored by dorit on Jun 25 2017, 1:26 AM.


[AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2

The cost of an interleaved access was only implemented for AVX512. For other
X86 targets an overly conservative Base cost was returned, resulting in
avoiding vectorization where it is actually profitable to vectorize.
This patch starts to add costs for AVX2 for most prominent cases of
interleaved accesses (stride 3,4 chars, for now).

Note1: Improvements of up to ~4x were observed in some of EEMBC's rgb
workloads; There is also a known issue of 15-30% degradations on some of these
workloads, associated with an interleaved access followed by type
promotion/widening; the resulting shuffle sequence is currently inefficient and
will be improved by a series of patches that extend the X86InterleavedAccess pass
(such as D34601 and more to follow).

Note 2: The costs in this patch do not reflect port pressure penalties which can
be very dominant in the case of interleaved accesses since most of the shuffle
operations are restricted to a single port. Further tuning, that may incorporate
these considerations, will be done on top of the upcoming improved shuffle
sequences (that is, along with the abovementioned work to extend
X86InterleavedAccess pass).

Differential Revision: https://reviews.llvm.org/D34023

llvm-svn: 306238


doritJun 25 2017, 1:26 AM
Differential Revision
D34023: [AVX2] [TTI CostModel] Add cost of interleaved loads/stores for AVX2
rG3370e19725fb: Add support for Ananas platform